Verilog Language Support Exceptions - 2022.1 English

The module_or_generate_item alternative is not supported.

Production from IEEE standard (see IEEE Standard Verilog Hardware Description Language (IEEE-STD-1364-2001) section 13.2 ):

generate_item_or_null ::= 
generate_conditonal_statement |
generate_case_statement |
generate_loop_statement |
generate_block |
module_or_generate_item

Production supported by Simulator:

generate_item_or_null ::=
generate_conditional_statement|
generate_case_statement |
generate_loop_statement |
generate_blockgenerate_condition

Partially supported.

All generate blocks must be named.

Production from standard (see IEEE Standard Verilog Hardware Description Language (IEEE-STD-1364-2001) section 13.2):

generate_block ::=
begin
[ : generate_block_identifier ]
{ generate_item }
end

Production supported by Simulator:

generate_block ::=
begin:
generate_block_identifier {
generate_item }
end

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