Customizing the Waveform - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID: UG900
Release Date: 2022-04-21
Version: 2022.1 English

Overview
Navigating Content by Design Process
Logic Simulation Overview
Supported Simulators
Simulation Flow
Behavioral Simulation at the Register Transfer Level
Post-Synthesis Simulation
Post-Implementation Simulation
Language and Encryption Support
Preparing for Simulation
Using Test Benches and Stimulus Files
Pointing to the Simulator Install Location
Compiling Simulation Libraries
Compiling Simulation Libraries Using Vivado IDE
Compiling Simulation Libraries Using Tcl Commands
Changing compile_simlib Defaults
Using Xilinx Simulation Libraries
UNISIM Library
UNIMACRO Library
SIMPRIM Library
SECUREIP Simulation Library
UNIFAST Library
Using Verilog UNIFAST Library
Using VHDL UNIFAST Library
Using Simulation Settings
Understanding the Simulator Language Option
Setting the Simulation Runtime Resolution
Adding or Creating Simulation Source Files
Working with Simulation Sets
Generating a Netlist
Generating a Functional Netlist
Generating a Timing Netlist
Using Versal CIPS VIP
Simulating with Third-Party Simulators
Running Simulation Using Third Party Simulators with Vivado IDE
Running Timing Simulation Using Third-Party Tools
Dumping SAIF for Power Analysis
Dumping SAIF in Questa Advanced Simulator/ModelSim
Dumping SAIF in VCS
Dumping VCD
Dumping VCD in Questa Advanced Simulator/ModelSim
Dumping VCD in VCS
Simulating IP
Using a Custom DO File During an Integrated Simulation Run
In Questa Advanced Simulator
In Modelsim
In VCS
In Xcelium
Simulation Step Control Constructs for ModelSim and Questa Advanced Simulator
Running Third-Party Simulators in Batch Mode
Simulating with Vivado Simulator
Running the Vivado Simulator
Main Toolbar
Run Menu
Simulation Toolbar
Sources Window
Scope Window
Objects Window
Wave Window
Wave Objects
Creating and Using Multiple Waveform Configurations
Running Functional and Timing Simulation
Running Functional Simulation
Running Timing Simulation
Saving Simulation Results
Distinguishing Between Multiple Simulation Runs
Closing a Simulation
Adding a Simulation Start-up Script File
Viewing Simulation Messages
Managing Message Output
Using the launch_simulation Command
Examples
Re-running the Simulation After Design Changes (relaunch)
Using the Saved Simulator User Interface Settings
Default Settings
Analyzing Simulation Waveforms with Vivado Simulator
Using Wave Configurations and Windows
Creating a New Wave Configuration
Opening a WCFG File
Saving a Wave Configuration
Opening a Previously Saved Simulation Run
Understanding HDL Objects in Waveform Configurations
About Radixes
Changing the Default Radix
Changing the Radix on Individual Objects
Customizing the Waveform
Using Analog Waveforms
Waveform Object Naming Styles
Renaming Objects
Changing the Object Display Name
Reversing the Bus Bit Order
Changing the Format of SystemVerilog Enumerations
Controlling the Waveform Display
Using the Column Resizing Handles
Scrolling with the Mouse Wheel
Using the Zoom Feature Buttons
Zooming with the Mouse Wheel
Y-Axis Zoom Gestures for Analog Waveforms
Using the Waveform Settings Dialog Box
Changing the Display of the Time Scale
Organizing Waveforms
Grouping Signals and Objects
Using Dividers
Defining Virtual Buses
Analyzing Waveforms
Using Cursors
Using Markers
Using the Floating Ruler
Searching a Value in Waveform Configuration
Analyzing AXI Interface Transactions
Understanding Protocol Instances
Using the IP Integrator to Mark an AXI Interface to View in the Vivado Simulator
Finding Protocol Instances in the Vivado Simulator
Finding Protocol Instances in the Objects Window
Finding Protocol Instances Using a Tcl Command
Protocol Instance in the Objects Window
Adding Protocol Instances to the Wave Window
Using get_objects Programmatically
Analyzing Protocol Instances in the Wave Window
Using Transaction Bars
Analyzing AXI Memory-Mapped (AXI-MM) Interfaces
Analyzing AXI4-Stream (AXI-S) Interfaces
Debugging a Design with Vivado Simulator
Debugging at the Source Level
Stepping Through a Simulation
Using Breakpoints
Adding Conditions
Pausing a Simulation
Tracing the Execution of a Simulation
Forcing Objects to Specific Values
Using Force Commands
Force Constant
Force Clock
Remove Force
Using Force in Batch Mode
Power Analysis Using Vivado Simulator
Generating SAIF Dumping
Example SAIF Tcl Commands
Dumping SAIF using a Tcl Simulation Batch File
Using the report_drivers Tcl Command
Using the Value Change Dump Feature
Using the log_wave Tcl Command
Cross Probing Signals in the Object, Wave, and Text Editor Windows
Tool Specific init.tcl
Subprogram Call-Stack Support
Simulating in Batch or Scripted Mode in Vivado Simulator
Exporting Simulation Files and Scripts
Exporting the Top Level Design
Exporting IP from the Xilinx Catalog and Block Designs
Exporting a Manage IP Project
Running the Vivado Simulator in Batch Mode
Parsing Design Files, xvhdl and xvlog
Elaborating and Generating a Design Snapshot, xelab
xelab
xelab Examples
Verilog Search Order
Verilog Instantiation Unit
VHDL Instantiation Unit
`uselib Verilog Directive
xelab, xvhdl, and xvlog xsim Command Options
Simulating the Design Snapshot, xsim
xsim Executable Syntax
xsim Executable Options
Functional Coverage Report Generator
Example of Running Vivado Simulator in Standalone Mode
Step 1: Analyzing the Design File
Step 2: Elaborating and Creating a Snapshot
Step 3: Running Simulation
Project File (.prj) Syntax
Predefined Macros
Library Mapping File (xsim.ini)
Running Simulation Modes
Behavioral Simulation
Running Post-Synthesis and Post-Implementation Simulations
Using Tcl Commands and Scripts
Using a -tclbatch File
Launching Vivado Simulator from the Tcl Console
export_simulation
export_ip_user_files
Compilation, Elaboration, Simulation, Netlist, and Advanced Options
Compilation Options
Vivado Simulator Compilation Options
Questa Advanced Simulator Compilation Options
ModelSim Simulator Compilation Options
VCS Simulator Compilation Options
Xcelium Simulator Compilation Options
Elaboration Options
Vivado Simulator Elaboration Options
Questa Advanced Simulator Elaboration Options
ModelSim Simulator Elaboration Options
VCS Simulator Elaboration Options
Xcelium Simulator Elaboration Options
Simulation Options
Vivado Simulator Simulation Options
Questa Advanced Simulator Simulation Options
ModelSim Simulator Simulation Options
VCS Simulator Simulation Options
Xcelium Simulator Simulation Options
Netlist Options
Vivado Simulator Netlist Options
Advanced Simulation Options
SystemVerilog Support in Vivado Simulator
Targeting SystemVerilog for a Specific File
Running SystemVerilog in Standalone or prj Mode
Testbench Feature
Universal Verification Methodology Support
VHDL 2008 Support in Vivado Simulator
Introduction
Compiling and Simulating
Fixed and Floating Point Packages
Supported Features
Direct Programming Interface (DPI) in Vivado Simulator
Introduction
Compiling C Code
xsc Compiler
Binding Compiled C Code to SystemVerilog Using xelab
Data Types Allowed on the Boundary of C and SystemVerilog
Supported Data Types
Mapping for User-Defined Types
Enum
Packed Struct/Union
Unpacked Struct
Support for svdpi.h Functions
Open Arrays in DPI
Examples
Import Example Using -sv_lib, -sv_liblist, and -sv_root
Function with Output
Simple Import-Export Flow (Illustrates xelab -dpiheader Flow)
DPI Examples Shipped with the Vivado Design Suite
SystemC Support in Vivado IDE
Selecting Simulation Model Type
Using SELECTED_SIM_MODEL IP Property
Using PREFERRED_SIM_MODEL Project Property
Protected Models
Unprotected Models
SystemC Simulation Using Vivado
Simulators Supported for SystemC Simulation
Simulator Settings for Third-Party Tools
GCC Path Settings
Running SystemC Simulation Using Vivado Simulator
Automated Testbench Generation for Sub-Design
generate_vcd_ports
create_testbench
Using Automated Testbench Generation on Example Design
Handling Special Cases
Using Global Reset and 3-State
Global Set and Reset Net
Global 3-State Net
Using Global 3-State and Global Set and Reset Signals
Global Set and Reset and Global 3-State Signals in Verilog
Global Set and Reset and Global 3-State Signals in VHDL
Delta Cycles and Race Conditions
VHDL Coding Example With Unexpected Results
Using the ASYNC_REG Constraint
Disabling X Propagation for Synchronous Elements
Simulating Configuration Interfaces
JTAG Simulation
SelectMAP Simulation
Disabling Block RAM Collision Checks for Simulation
Dumping the Switching Activity Interchange Format File for Power Analysis
Skipping Compilation or Simulation
Skipping Compilation
Skipping Simulation
Value Rules in Vivado Simulator Tcl Commands
String Value Interpretation
Vivado Design Suite Simulation Logic
Vivado Simulator Mixed Language Support and Language Exceptions
Using Mixed Language Simulation
Restrictions on Mixed Language in Simulation
Key Steps in a Mixed Language Simulation
Mixed Language Binding and Searching
Instantiating Mixed Language Components
Port Mapping and Supported Port Types
Generics (Parameters) Mapping
VHDL and Verilog Values Mapping
VHDL Language Support Exceptions
Verilog Language Support Exceptions
Vivado Simulator Quick Reference Guide
Using Xilinx Simulator Interface
Preparing the XSI Functions for Dynamic Linking
Writing the Test Bench Code
Compiling Your C/C++ Program
Preparing the Design Shared Library
XSI Function Reference
xsi_close
xsi_get_error_info
xsi_get_port_number
xsi_get_status
xsi_get_value
xsi_open
xsi_put_value
xsi_restart
xsi_run
xsi_trace_all
Vivado Simulator VHDL Data Format
IEEE std_logic Type
VHDL bit Type
VHDL Character Type
VHDL integer Type
VHDL real Type
VHDL Array Types
Vivado Simulator Verilog Data Format
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Links to Additional Information on Third-Party Simulators
Training Resources
Revision History
Please Read: Important Legal Notices

Back to home page