export_simulation - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID

UG900

Release Date

2022-04-21

Version

2022.1 English

Export a simulation script file for the target simulator. The generated script will contain simulator commands for compiling, elaborating and simulating the design.

This command will retrieve the simulation compile order of specified objects, and export this information in a shell script with the compiler commands and default options for the target simulator. The specified object can be either a simulation fileset or an IP. If you want to run simulation outside Vivado IDE, export_simulation can be used in place of launch_simulation -scripts_only to generate scripts file.

export_simulation  [-simulator <arg>] [-of_objects <arg>]
                   [-ip_user_files_dir <arg>] [-ipstatic_source_dir <arg>]
                   [-lib_map_path <arg>] [-script_name <arg>]
                   [-directory <arg>] [-runtime <arg>] [-define <arg>]
                   [-generic <arg>] [-include <arg>] [-use_ip_compiled_libs]
                   [-absolute_path] [-export_source_files]
                   [-generate_hier_access] [-32bit] [-force] [-quiet]
                   [-verbose][-gcc_install_path <arg>] [-more_options <arg>]

Usage

Table 1. export_simulation Options
Name	Description
`[-simulator]`	Simulator for which the simulation script will be created. Allowed values are all, xsim, modelsim, questa, vcs, xcelium, riviera, and activehdl. Default: all
`[-of_objects]`	Export simulation script for the specified object. Default: None
`[-lib_map_path]`	Precompiled simulation library directory path. If not specified, follow the instructions in the generated script header to manually provide the simulation library mapping information. Default: Empty
`[-script_name]`	Output shell script filename. If not specified, then file with a default name will be created. Default: top_module.sh
`[-directory]`	Directory where the simulation script will be generated. Default: export_sim
`[-runtime]`	Run simulation for this time. Default: full simulation run or until a logical break or finish condition
`[-absolute_path]`	Make all file paths absolute with respect to the reference directory.
`[-export_source_files]`	Copy IP/BD design files to output directory.
`[-32bit]`	Perform 32-bit compilation.
`[-force]`	Overwrite previous files.
`[-quiet]`	Ignore command errors.
`[-verbose]`	Suspend message limits during command execution.
`[-ip_user_files_dir]`	Directory path to exported IP/BD user files (for static, dynamic and data files). Default: Empty
`[-ipstatic_source_dir]`	Directory path to the exported IP/BD static files. Default: Empty
`[-define]`	Read Verilog defines from the list specified with this switch. Default: Empty
`[-generic]`	Read VHDL generics from the list specified with this switch. Default: Empty
`[-include]`	Read include directory paths from the list specified with this switch. Default: Empty
`[-use_ip_compiled_libs]`	Reference pre-compiled IP static library during compilation. This switch requires `-ip_user_files_dir` and `-ipstatic_source_dir` switches also for generating scripts using pre-compiled IP library.
`[-generate_hier_access]`	Extract path for hierarchical access simulation
`[-gcc_install_path]`	GNU compiler installation directory path for the g++/gcc executables. Default: Empty
`[-more_options]`	Pass specified options to the simulator tool. Default: Empty

Description

Export a simulation script file for the target simulator (please see the list of supported simulators below). The generated script will contain simulator commands for compiling, elaborating and simulating the design.

The command will retrieve the simulation compile order of specified objects, and export this information in a shell script with the compiler commands and default options for the target simulator. The specified object can be either a simulation fileset, IP or a BD (block design).

If the object is not specified, then this command will generate the script for the active simulation top. Any Verilog include directories or file paths for the files containing Verilog define statements will be added to the compiler command line.

By default, the design source file and include directory paths in the compiler command line will be set relative to the reference_dir variable that is set in the generated script. To make these paths absolute, specify the -absolute_path switch.

The command will also copy data files (if any) from the fileset, or from an IP, to the output directory. If the design contains Verilog sources, then the generated script will also copy the glbl.v file from the software installation path to the output directory.

A default .do file that is used in the compiler commands in the simulation script for the target simulator, will be written to the output directory.

Note: In order to perform simulation with the generated script, the simulation libraries must be compiled first using the compile_simlib Tcl command. The compiled library directory path must be specified when generating this script. The generated script will automatically include the setup files for the target simulator from the compiled library directory.

Supported Simulators

Vivado simulator (xsim)
ModelSim Simulator (modelsim)
Questa Advanced Simulator (questa)
Verilog Compiler Simulator (vcs)
Riviera-PRO Simulator (riviera)
Active-HDL Simulator (activehdl)
Cadence Xcelium Parallel Simulator (xcelium)

Arguments

-of_objects

(Optional) Specify the target object for which the simulation script file needs to be generated. The target object can be either a simulation fileset (simset) or an IP. If this option is not specified then this command will generate file for the current simulation fileset.

-lib_map_path

(Optional) Specify path to the Xilinx pre-compiled simulation library for the selected simulator. The simulation library is compiled using compile_simlib. See the header section in the generated script for more information. If this switch is not specified, then the generated script will not reference the pre-compiled simulation library and the static IP files will be locally compiled.

-script_name

(Optional) Specify name of the generated script. Default name is <simulation_top>.sh. If the -of_objects switch is specified, then the default syntax of the script will be as follows:


-of_objects [current_fileset -simset] .sh
-of_objects [get_ips ] .sh
-of_objects [get_files .xci] .sh
-of_objects [get_files .bd] .sh

-absolute_path

(Optional) Specify this option to make source and include directory paths absolute. By default, all paths are set relative to the output directory specified with the -directory switch.

-32bit

(Optional) Specify this option to perform 32-bit simulation. If this option is not specified then by default 64-bit option will be added to the simulation command line.

-force

(Optional) Overwrite an existing script file of the same name. If the script file already exists, the tool returns an error unless the -force argument is specified.

-directory

(Required) Specify the directory path where the script file will be exported.

-simulator

(Required) Specify the target simulator name for the simulation script. The valid simulators names are xsim, modelsim, questa, and vcs (or vcs_mx).

-quiet

(Optional) Execute the command quietly, ignoring any command line errors and returning no messages. The command also returns TCL_OK regardless of any errors encountered during execution.

-verbose

(Optional) Temporarily override any message limits and return all messages from this command.

-generate_hier_access

(Optional) Extract path for hierarchical access simulation.

-runtime

(Optional) Specify simulation run-time.

-define

(Optional) Specify the list of verilog defines used in the design.

-generic

(Optional) Specify the list of VHDL generics used in the design.

-include

(Optional) Specify the list of include directory paths for verilog include files in the design.

-export_source_files

(Optional) Specify this option to copy the IP design files to the generated script directory in a sub-directory named srcs. The generated script will reference the design files from this srcs directory.