Automated Testbench Generation for Sub-Design - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.1 English

From 2021.2 onwards, new methodology is introduced in Vivado simulator (XSim) to create a realistic functional testbench for a language independent sub-design unit. This methodology currently works for Verilog/VHDL/System Verilog and mixed design of these language. To use this methodology, two new Tcl commands are introduced. Usage of this new methodology with a real design is explained in subsequent sections.