ModelSim Simulator Compilation Options - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-04-21
Version
2022.1 English
Table 1. ModelSim Compilation Options
Option Description
Verilog options Browse to set Verilog include path and to define macro
Generics/Parameters options Specify or browse to set the generic/parameter value
modelsim.compile.tcl.pre TCL file containing set of commands that should be invoked before launch of compilation
modelsim.compile.vhdl_syntax Specify VHDL syntax
modelsim.compile.use_explicit_decl Log all signals
modelsim.compile.load_glbl Load GLBL module
modelsim.compile.vlog.more_options More VLOG compilation options
modelsim.compile.vcom.more_options More VCOM compilation options