create_testbench - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.1 English

Create testbench for a design unit instance. This command creates a functional system verilog based testbench for the scoped hierarchical instance. The testbench contains port/signal specification, parameter declaration, stimuli vector include file, and module instantiation of the selected instance as design under test (DUT). This command allows you to add the testbench to an existing or a new simulation fileset from which the simulation can be launched.

Note: The generated testbench is simulator independent.
Table 1. create_testbench Command Options
Option Description
-name <arg> Specify the name of the testbench module name. Default name is testbench.
-add_to_simset <arg> Specify simulation fileset name to which the testbench needs to be added. If this switch is not specified, then the command adds testbench to the current active simulation fileset.
-set_as_top Set the generated testbench module at the top in the simulation fileset where the testbench is added.
-mode <arg> Specifies simulation mode. Allowed values are behavioral, post-synthesis, or post-implementation. Default is behavioral.
-type <arg> Specifies simulation type. Allowed values are functional or timing (not applicable for behavioral mode).
-force Overwrite existing testbench file.
-quiet Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line while launching the command are returned. Only errors occurring inside the command are trapped.
-verbose Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.
  1. All the arguments are optional as default value is set as explained for each flag.

The following example command creates a testbench for fifo module and adds it to the sub_design_fifo simulation fileset:

create_testbench -name fifo -add_to_simset sub_design_fifo

The following example command generates VCD file for /top/DUT/fifo/buf_1 instance of type buf module, record the waveform activity in the VCD file for 2000ns, create a testbench with module named tb, add the testbench to the test_buffer simulation fileset and set tb as top module in this fileset:

generate_vcd_ports {/top/DUT/fifo/buf_1}
run 2000ns
close_vcd -ports
create_testbench -name tb -add_to_simset test_buffer -set_as_top