Data Types Allowed on the Boundary of C and SystemVerilog - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.1 English

The IEEE Standard for SystemVerilog allows only subsets of C and SystemVerilog data types on the C and SystemVerilog boundary. Provided below are (1) details on data types supported in Vivado simulator and (2) descriptions of mapping between the C and SystemVerilog data types.