Vivado Design Suite Simulation Logic - 2022.1 English

The logic is not a concept defined in HDL but is a heuristic introduced by the Vivado® simulator.

• A Verilog object is considered to be of logic type if it is of the implicit Verilog bit type, which includes wire and reg objects, as well as integer and time.
• A VHDL object is considered to be of logic type if the objects type is bit, std_logic, or any enumeration type whose enumerators are a subset of those of std_logic and include at least 0 and 1, or type of the object is a one-dimensional array of such a type.
• For HDL objects, which are of VHDL enumeration type, the value can be one of the enumerator literals, without single quotes if the enumerator is a character literal. Radix is ignored.
• For VHDL objects, of integral type, the value can be a signed decimal integer in the range of the type. Radix is ignored.
• For VHDL and Verilog floating point types the value can be a floating point value. Radix is ignored.
• For all other types of HDL objects, the Tcl command set does not support setting values.