Vivado Simulator Quick Reference Guide - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2022-04-21
Version
2022.1 English

The following table provides a quick reference and examples for common Vivado® simulator commands.

Table 1. Standalone Mode: Parsing, Elaborating, and Running Simulation from a Command Line
Parsing HDL Files
Vivado simulator supports three HDL file types: Verilog, SystemVerilog and VHDL. You can parse the supported files using XVHDL and XVLOG commands.
Parsing VHDL files

xvhdl file1.vhd file2.vhd

xvhdl -work worklib file1.vhd file2.vhd

xvhdl -prj files.prj

Parsing Verilog files

xvlog file1.v file2.v

xvlog -work worklib file1.v file2.v

xvlog -prj files.prj

Parsing SystemVerilog files

xvlog -sv file1.v file2.v

xvlog -work worklib -sv file1.v file2.v

xvlog -prj files.prj

For information about the PRJ file format, see Project File (.prj) Syntax.
Additional xvlog and xvhdl Options
xvlog and xvhdl Key Options

See Table 1 for a complete list of command options.

The following are key options for xvlog and xvhdl:
Key Option Applies to:
xelab, xvhdl, and xvlog xsim Command Options xvlog
xelab, xvhdl, and xvlog xsim Command Options xvlog, xvhdl
xelab, xvhdl, and xvlog xsim Command Options xvlog
xelab, xvhdl, and xvlog xsim Command Options xvlog, xvhdl
xelab, xvhdl, and xvlog xsim Command Options xvlog, xvhdl
xelab, xvhdl, and xvlog xsim Command Options xvlog, xvhdl
xelab, xvhdl, and xvlog xsim Command Options xvlog, xvhdl
xelab, xvhdl, and xvlog xsim Command Options xvhdl, vlog
xelab, xvhdl, and xvlog xsim Command Options xvlog, xvhdl
Elaborating and Generating an Executable Snapshot

After parsing, you can elaborate the design in Vivado simulator using the XELAB command. XELAB generates an executable snapshot.

You can skip the parser stage, directly invoke the XELAB command, and pass the PRJ file. XELAB calls XVLOG and XVHDL for parsing the files.
Usage xelab top1 top2 Elaborates a design that has two top design units: top1 and top2. In this example, the design units are compiled in the work library.
xelab lib1.top1 lib2.top2 Elaborates a design that has two top design units: top1 and top2. In this example, the design units have are compiled in lib1 and lib2, respectively
xelab top1 top2 -prj files.prj Elaborates a design that has two top design units: top1 and top2. In this example, the design units are compiled in the work library. The file files.prj contains entries such as: 
verilog <libraryName> 
<VerilogDesignFileName>
vhdl <libraryName> <VHDLDesignFileName>
sv <libraryName> 
<SystemVerilogDesignFileName>
xelab top1 top2 -s top Elaborates a design that has two top design units: top1 and top2. In this example, the design units are compiled in the work library. After compilation, xelab generates an executable snapshot with the name top. Without the -s top switch, xelab creates the snapshot by concatenating the unit names.
Command Line Help and xelab Options

xelab -help

Table 1

Running Simulation
After parsing, elaboration and compilation stages are successful; xsim generates an executable snapshot to run simulation.
Usage xsim top -R Simulates the design to through completion.
xsim top -gui Opens the Vivado simulator workspace (GUI).
xsim top Opens the Vivado Design Suite command prompt in Tcl mode. From there, you can invoke such options as: 
run -all 
run 100 ns
Important Shortcuts
You can invoke the parsing, elaboration, and executable generation and simulation in one, two, or three stages.
  Three Stage

xvlog bot.v

xvhdl top.vhd

xelab work.top -s top

xsim top -R

  Two Stage

xelab -prj my_prj.prj work.top -s top

xsim top -R

where my_prj.prj file contains:

verilog work bot.v

vhdl work top.vhd

  Single Stage

xelab -prj my_prj.prj work.top -s top -R

where my_prj.prj file contains:

verilog work bot.v vhdl work top.vhd

Note: If your design contain UVM construct then you need to pass -L uvm to xvlog and xelab command
Vivado Simulation Tcl Commands

The following are commonly used Tcl commands. For a complete list, invoke following commands in the Tcl Console:

load_features simulator

help -category simulation

For information on any Tcl Command, type: -help <Tcl_command>

Common Vivado Simulator Tcl Commands: add_bp Add break point at a line of HDL source.
add_force Force the value of a signal, wire, or register to a specified value. Tcl command exampled are provided on Using Force Commands.

current_time

now

Report current simulation time. See Using a -tclbatch File for an example of this command within a Tcl script.
current_scope Report or set the current, working HDL scope. See Scope Window for more information.
get_objects Get a list of HDL objects in one or more HDL scopes, per the specified pattern. For example command usage refer to: Example SAIF Tcl Commands.
get_scopes Get a list of child HDL scopes. See Scope Window for more information.
get_value Get the current value of the selected HDL object (variable, signal, wire, register). Type get_value -help in Tcl Console for more information.
launch_simulation Launch simulation using the Vivado simulator.
remove_bps Remove breakpoints from a simulation.
report_drivers Print drivers along with current driving values for an HDL wire or signal object. Reference for more information: Using the report_drivers Tcl Command.
report_values Print current simulated value of given HDL objects (variables, signals, wires, or registers). For example Tcl command usage, see Scope Window.
restart Rewind simulation to post loading state (as though the design was reloaded); time is set to 0.
set_value Set the HDL object (variable, signal, wire, or register) to a specified value. Reference for more information: Value Rules in Vivado Simulator Tcl Commands.
step Step simulation to the next statement. See Stepping Through a Simulation.