Vivado Design Suite - 2020.2 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

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2020.2 English

The Xilinx Vivado® Design Suite contains tools that are encapsulated in the Vivado integrated design environment (IDE). The IDE provides an intuitive graphical user interface (GUI) with powerful features.

The Vivado Design Suite supersedes the Xilinx ISE software with additional features for system-on-a-chip development and high-level synthesis. It delivers a SoC-strength, IP- and system-centric, next generation development environment built exclusively by Xilinx to address the productivity bottlenecks in system-level integration and implementation.

All of the tools and tool options in Vivado Design Suite are written in native Tool Command Language (Tcl) format, which enables use both in the Vivado IDE or the Vivado Design Suite Tcl shell. Analysis and constraint assignment is enabled throughout the entire design process. For example, you can run timing or power estimations after synthesis, placement, or routing. Because the database is accessible through Tcl, changes to constraints, design configuration, or tool settings happen in real time, often without forcing re-implementation.

The Vivado IDE uses a concept of opening designs in memory. Opening a design loads the design netlist at that particular stage of the design flow, assigns the constraints to the design, and then applies the design to the target device. This provides the ability to visualize and interact with the design at each design stage.

Important: The Vivado IDE supports designs that target 7 series and newer devices only.

You can improve design performance and ease of use through the features delivered by the Vivado Design Suite, including:

  • The Processor Configuration Wizard (PCW) within the IP integrator with graphical user interfaces to let you create and modify the PS within the IP integrator block design.
    Video: For a better understanding of the PCW, see the Quick Take Video: Vivado Processor Configuration Wizard Overview.
  • Register transfer level (RTL) design in VHDL, Verilog, and SystemVerilog.
  • Quick integration and configuration of IP cores from the Xilinx IP catalog to create block designs through the Vivado IP integrator.
  • Vivado synthesis.
  • C-based sources in C, C++, and SystemC.
  • Vivado implementation for place and route.
  • Vivado serial I/O and logic analyzer for debugging.
  • Vivado power analysis.
  • SDC-based Xilinx Design Constraints (XDC) for timing constraints entry.
  • Static timing analysis.
  • Flexible floorplanning.
  • Detailed placement and routing modification.
  • Bitstream generation.
  • Vivado Tcl Store, which you can use to add to and modify the capabilities in Vivado.

You can download the Vivado Design Suite from the Xilinx Vivado Design Suite – HLx Editions.