Hardware Architecture Overview - 2020.2 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID
Release Date
2020.2 English

The Zynq UltraScale+ MPSoCs provide power savings, programmable acceleration, I/O, and memory bandwidth. These features are ideal for applications that require heterogeneous multiprocessing.

The following figure shows the Zynq UltraScale+ MPSoC architecture with next-generation programmable engines for security, safety, reliability, and scalability.

Figure 1. Zynq UltraScale+ MPSoC Device Hardware Architecture

The Zynq UltraScale+ MPSoC features are as follows:

  • Cortex-R5F dual-core real-time processor unit (RPU)
  • Arm Cortex-A53 64-bit quad/dual-core processor unit (APU)
  • Mali-400 MP2 graphic processing unit (GPU)
  • External memory interfaces: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3, 2x Quad-SPI, and NAND
  • General connectivity: 2x USB 3.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 1GE, and GPIO
  • Security: Advanced Encryption Standard (AES), RSA public key encryption algorithm, and Secure Hash Algorithm-3 (SHA-3)
  • AMS system monitor: 10-bit, 1 MSPS ADC, temperature, voltage, and current monitor
  • The processor subsystem (PS) has five high-speed serial I/O (HSSIO) interfaces supporting the protocols:
    • PCIe┬« : base specification, version 2.1 compliant, and Gen2x4
    • SATA 3.0
    • DisplayPort: Implements a DisplayPort source-only interface with video resolution up to 4k x 2k
    • USB 3.0: Compliant to USB 3.0 specification implementing a 5 Gb/s line rate
    • Serial GMII: Supports a 1 Gb/s SGMII interface
  • Platform Management Unit (PMU) for functions that include power sequencing, safety, security, and debug.

For more details, see the following sections of the Zynq UltraScale+ Device Technical Reference Manual (UG1085): APU, RPU, PMU, GPU, and inter-processor interrupt (IPI).