In this stage, protection_config functions from
psu_init will be executed and then, any handoff functionality is
executed. Also PS-PL isolation is removed unconditionally. R5 will be brought out of
reset if there is any partition supposed to run on its cores. R5-0/R5-1 will be
configured to boot in lowvec mode or highvec mode as per the settings provided by you
while building the boot image. The handoff address in lowvec mode is
0x0 and 0xffff0000 in highvec mode. Lowvec/Highvec
information should be specified by you while building the boot image. After all the
other PS images are done, then the running CPU will be handed off with an update of the
PC value. If there is no image to hand off for the running the CPU, FSBL will be in wfe
loop.
Any running processor cannot pass any parameters to any other processor. Any communication between various partitions can happen by reading from (or writing to) the PMU global registers.
Handoff on the running processor involves updating Program Counter (PC) of the running processor, as is done in the case of APU Reset. Handoff to other processors involves updating their PCs and bringing the processors out of reset.
XFsbl_PmInit
This function initializes and configures the Inter Processor Interrupts (IPI). It then writes the PM configuration object address to an IPI buffer and triggers an IPI to the target. The PMU firmware then reads and configures the device nodes as specified in the configuration object.
Protection Configuration
In this stage, protection_config functions from
psu_init will be executed. The application of protection
happens in this stage.
Handoff
Handoff on the running processor involves updating Program Counter (PC) of the
running processor, as is done in the case of APU Reset. Handoff to other processors
involves updating their PCs and bringing the processors out of reset. A53 FSBL will
bring R5 out of reset if there is any partition to run on it. R5 will be configured
to boot in lowvec mode or highvec mode as per the settings provided by you while
building the boot image. The handoff address in lowvec mode is 0x0
and 0xffff0000 in highvec mode.
You must specify Lowvec/Highvec information while building the boot image. After all the other PS images are done, then running the CPU image will be handed off to that cpu with an update on the PC value. If there no image for the running CPU, it will be in wfe loop.
Supported Handoffs
The following table shows the various combinations of handoffs that are supported in FSBL.
| FSBL | Application | Processor Cores | Execution Address |
|---|---|---|---|
| 64-bit | 64-bit | All (i.e. A53-0, A53-1, A53-2, A53-3) | Any Address |
| 64-bit | 32-bit | A53-1, A53-2, A53-3 | 0x0 |
| 32-bit | 32-bit | A53-0 | Any Address |
| 32-bit | 32-bit | A53-1, A53-2, A53-3 | 0x0 |
| 32-bit | 64-bit | A53-1, A53-2, A53-3 | Any Address |
Error Lock Down
XFsbl_ErrorLockDown function handles errors in FSBL. This function
is called whenever the return value of a function is unsuccessful. This function
updates error status register and then loops indefinitely, if fallback is not
supported.
In case the boot mode supports fallback, MultiBoot offset register is updated and then waits for a WDT reset to occur. On reboot, bootROM and FSBL read the image from the new address calculated from MultiBoot offset, thus loading a new image.
