Initialization - 2020.2 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID
Release Date
2020.2 English

Initialization consists of the following four internal stages:


This function powers up PL for 1.0 and 2.0 silicon and removes PS-PL isolation. It initializes clocks and peripherals as specified in psu-init. This function is not called in APU only reset.

Figure 1. FSBL System Initialization


Processor initialization will start in this stage. It will set up the Instruction and Data caches, L2 caches, MMU settings, stack pointers in case of A53 and I/D caches, MPU settings, memory regions, stack pointers, and TCM settings for R5-0. Most of these settings will be performed in BSP code initialization. IVT vector is changed to the start of OCM for A53 and to start of TCM (0x0 in lowvec and 0xffff0000 in highvec) in case of R5-0.

Figure 2. Processor Initialization

Initialize DDR

DDR would be initialized in this stage. This function is not called in Master only reset.

Figure 3. DDR Initialization


This function performs required board specific initializations. Most importantly, it configures GT lanes and IIC.

Figure 4. Board Initialization