Zynq UltraScale+ MPSoC Power Management Hardware Architecture - 2020.2 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

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2020.2 English

The Zynq UltraScale+ MPSoC is divided into four major power domains:

  • Full power domain (FPD): Contains the Arm® Cortex™-A53 application processor unit (APU) as well as a number of peripherals typically used by the APU.
  • Low power domain (LPD): Contains the Arm Cortex™-R5F real-time processor unit (RPU), the platform management unit (PMU), and the configuration security unit (CSU), as well as the remaining on-chip peripherals.
  • Programmable logic (PL) power domain: Contains the PL.
  • Battery-power domain: Contains the real-time clock (RTC) as well as battery-backed RAM (BBRAM).

Other power domains listed in the following figure are not actively managed by the power framework. Designs that want to take advantage of the Power Management switching of power domains must keep some power rails discrete. This allows individual rails to be powered off with the power domain switching logic. For more details, see the “PCB Power Distribution and Migration in UltraScale+ FPGAs” in the UltraScale Architecture PCB Design User Guide (UG583).

The following diagram illustrates the Zynq UltraScale+ MPSoC power domains and islands.

Figure 1. Zynq UltraScale+ MPSoC Power Domain and Islands

Because of the heterogeneous multi-core architecture of the Zynq UltraScale+ MPSoC, no single processor can make autonomous decisions about power states of individual components or subsystems.

Instead, a collaborative approach is taken, where a power management API delegates all power management control to the platform management unit (PMU). It is the key component coordinating the power management requests received from the other processing units (PUs), such as the APU or the RPU, and the coordination and execution from other processing units through the power management API.

Important: In the EEMI implementation for Zynq UltraScale+ MPSoC, the platform management unit (PMU) serves as the power management controller for the different processor units (PUs), such as the APU and the RPU. These APU/RPU act as a power management (PM) master node and make power management requests. Based on those requests, the PMU controls the power states of all PM slave nodes as well as the PM masters. Unless otherwise specified, the terms "PMU" and "power management controller" are interchangeable.

The Zynq UltraScale+ MPSoC also supports inter-processor interrupts (IPIs), which are used as the basis for power-management related communication between the different processors. See this link to the “Interrupts” chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more detail on this topic.