Platform Management for Interconnects - 2020.2 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

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2020.2 English

The Interconnect lays across multiple power rails and power islands which can be on or off at different times. To ease the implementation, in most cases, the clocks for two power domains that communicate with one another must be asynchronous; consequently, requiring synchronizers on their interconnection.

To ease timing, the power domain is placed exactly at the clock crossing. The synchronizer must be implemented as two separate pieces with each placed in one of the two domains that are connected through the synchronizer, creating a bridge.

The bridge consists of a slave interface and a master interface with each lying entirely within a single power and clock domain. The clock frequencies at the interfaces can vary independent of each other, and each half can be reset independent of the other half.

Level shifters or clamping, or both, must be implemented between the two halves of the bridge for multi-voltage implementation or power-off.

Also, the bridge keeps track of open transactions, as follows:

  • When the bridge receives a power-down request from the PMU, it logs that request.
  • All new transactions return an error while the previously open transactions are being processed as usual until the transaction counter becomes 0. At that point, the bridge acknowledges to the PMU that it is safe to shut down the master or slave connected to the bridge.
  • The entire Interconnect shuts down only when all bridges within that interconnect are idle.

For more details, see this link to the “PMU Interconnect” sub-section in the “Platform Management Unit” chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).