This section describes the multimedia software stack in the Zynq UltraScale+ MPSoC.
The GPU and a high performance DisplayPort accelerate the graphics application. The GPU provides hardware acceleration for 2D and 3D graphics by including one geometry processor (GP) and two pixel processors (PP0 and PP1), each having a dedicated memory management unit (MMU). The cache coherency between the APU and the GPU is achieved by cache-coherent interconnect (CCI), which supports the AXI coherency extension (ACE) only.
CCI in-turn connects the APU and the GPU to the DDR controller, which arbitrates the DDR access.
The following figure shows the multimedia stack.
The Linux kernel drivers for multimedia enables the hardware access by the applications running on the processors.
The following table lists the multimedia drivers through the middleware stack that consists of the libraries and framework components the applications use.
| Component | Description |
|---|---|
| Display server | Coordinates the input and output from the applications to the operating system. |
| Graphics library | The Zynq UltraScale+ MPSoC architecture supports OpenGL ES 1.1 and 2.2, and Open VG 1.1. |
| Mali™ -400 MP2 common libraries | Mali-400 MP2 graphic libraries. For more details on how to switch between different EGL backends, refer to Xilinx MALI Driver. |
| Gstreamer | A freeware multimedia framework that allows a programmer to create a variety of media handling components. |
| Video codecs | Video encoders and decoders. |
The following table lists the Linux kernel graphics drivers.
| Drivers | Description |
|---|---|
| Frame buffer driver | Kernel graphics driver exposing its interface through /dev/fb*. This interface implements limited functionality (allowing you to set a video mode and drawing to a linear frame buffer). |
| Direct rendering manager (DRM) | Serves in rendering the hardware between multiple user space components. |
| Mali-400 MP2 graphics drivers | Provides the hardware access to the GPU hardware. |
| Video drivers | Video capture and output device pipeline drivers
based on the V4L2 framework. The Xilinx Linux V4L2 pipeline driver represents the
whole pipeline with multiple sub-devices. You can configure the
pipeline through the media node, and you can perform control
operations, such as stream on/off, through the video node. Device nodes are created be the pipeline driver. The pipeline driver also includes the wrapper layer of the DMA engine API, and this enables it to read/write frames from RAM. |
| Display port drivers | Enables the hardware access to the display port, based on DRM framework. |