Example for Error Management (PoR as a Response to Error) - 2020.2 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID
Release Date
2020.2 English

Some error may be too fatal and the system recovery from those errors may not be feasible without doing a Reset of entire system. In such cases PoR or SRST can be used as actions. In this example we use PoR reset as a response to the OCM ECC double-bit error.

Here is the code that adds the PoR as action:

@@ -162,6 +162,8 @@ static void EmCfgInit(const XPfw_Module_t *ModPtr, const u32
 if (XPfw_RecoveryInit() == XST_SUCCESS) {
 /* This is to enable FPD WDT and enable recovery mechanism when

The Tcl script to inject OCM ECC error is same as the one for above example. Once you trigger the error, a PoR occurs and you may see that all processors are in reset state similar to how they would be in a fresh power-on state. PMU RAM also gets cleared off during a PoR. Hence, PMU firmware needs to be reloaded.