System-Level Reset - 2020.2 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID
Release Date
2020.2 English

The Zynq UltraScale+ MPSoCs let you reset individual blocks such as the APU, RPU, or even individual power domains like the FPD and LPD. There are multiple, system-level reset options, as follows:

  • Power-on reset (POR)
  • System reset (SRST_B)
  • Debug system reset
For more details on the system-level reset flow, see this link to the “Reset System” chapter in the Zynq UltraScale+ Device Technical Reference Manual (UG1085).