RX Debug - 2.6 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

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2.6 English

Consult the port list section for a description of the diagnostic signals which are available to debug the RX.


This signal indicates that the receiver has detected and locked to the word boundaries as defined by a 01 or 10 control or data header. This is the first step to ensure that the 1G/10G/25G Ethernet Subsystem IP is functioning normally.

Under some conditions of no signal input, the SerDes receiver exhibits a steady pattern of alternating 1010101.... This can cause erroneous block lock, but still indicates that the receiver has detected the pattern.


A bad FCS indicates a bit error in the received packet. An FCS error could be due to any number of causes of packet corruption such as noise on the line.


A local fault indication can be locally generated or received. Some causes of a local fault are:

  • block lock not complete
  • high bit error rate
  • overflow or underflow

Loopback Check

If the Ethernet packets are being transmitted properly according to IEEE Std. 802.3, there should not be RX errors. However, the signal integrity of the received signals must be verified first.

To aid in debug, a local loopback can be performed with the signal ctl_local_loopback. This connects the TX SerDes to the RX SerDes, effectively bypassing potential signal integrity problems. The transceiver is placed into "PMA loopback", which is fully described in the transceiver product guide. In this way, the received data can be checked against the transmitted packets to verify that the logic is operating properly