The following table shows the XGMII/GMII Interface ports. These ports are available for the Ethernet PCS/PMA 32-bit core configuration only.
Name | I/O | Description | Clock Domain |
---|---|---|---|
rx_mii_d[31:0] | O | Receive XGMII Data bus. | rx_mii_clk |
rx_mii_c[3:0] | O | Receive XGMII Control bus. | rx_mii_clk |
rx_mii_clk | I | Receive XGMII Clock input. | See Clocking for more information. |
tx_mii_d[31:0] | I | Transmit XGMII Data bus. | rx_mii_clk |
tx_mii_c[3:0] | I | Transmit XGMII Control bus. | rx_mii_clk |
tx_mii_clk | I | Transmit XGMII Clock input. | See Clocking for more information. |
gmii_rxd[7:0] | O | Receive GMII Data bus. | rx_core_clk |
gmii_rx_dv | O | Receive GMII Control signal. | rx_core_clk |
gmii_rx_er | O | Receive GMII error signal. | rx_core_clk |
gmii_txd[7:0] | O | Transmit GMII Data bus. | tx_out_clk |
gmii_tx_en | O | Transmit GMII enable signal. | tx_out_clk |
gmii_rx_er | O | Transmit GMII error signal. | tx_out_clk |