These sub blocks contain per port TX and RX timers that are typically clocked by their
respective TX and RX PHY clocks (tx_phy_clk and
rx_phy_clk). The timer synchronizer IP allows for a maximum of
sixteen port timers to be enabled at the time of IP generation.
These port timers maintain time in both the ToD (48-bit seconds and 30-bits nano-sec) and
continuous time/correction field (63-bits CF) formats, and provide outputs synchronized
to the tx_phy_clk and rx_phy_clk for use by Xilinx’s Ethernet IP.
It is expected that each port’s TX and RX clock domains can be asynchronous with respect
to the Master timer’s ts_clk clock. The port timers contain
synchronization logic to domain cross the PTP System Timer’s load-pulse and timer update
values.
As the PTP System Timer is initialized, or synchronized to a high precision reference clock, it in turn pushes its updated timer value to all the port timers that are connected to it. After initialization, the Timer Syncer IP can be configured such that the port timers are continuously kept in-sync with the PTP System Timer’s master ToD value, or the port timers may be independently controlled.