stat_rx_bad_fcs[1:0] - 2.6 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

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2.6 English

When this signal is positive, it indicates that the error detection logic has identified mismatches between the expected and received value of CRC32 in the received packet. When a CRC32 error is detected, the received packet is marked as containing an error and is sent with rx_errout asserted during the last transfer (the cycle with rx_eopout asserted), unless ctl_rx_ignore_fcs is asserted. This signal is asserted for one clock period for each CRC32 error detected.