| Name | I/O | Description | Clock Domain |
|---|---|---|---|
| rx_clk_out | O |
Receive AXI4-Stream clock. All signals between the 1G/10G/25G Ethernet Subsystem and the user-side logic are synchronized to the positive edge of this signal. This clock is 125 MHz for 1G configuration, 156.25 / 312.5 MHz for 10G core configuration and 390.625 MHz for 25G configuration. |
See Clocking. |
| tx_clk_out | O |
Transmit AXI4-Stream clock. All signals between the 1G/10G/25G Ethernet Subsystemand the user-side logic are synchronized to the positive edge of this signal. This clock is 125 MHz for 1G configuration, 165.25 / 312.5 MHz for 10G core configuration and 390.625 MHz for 25G configuration. |
See Clocking. |
| rx_reset | I | Reset for the RX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The core handles synchronizing the rx_reset input to the appropriate clock domains within the core. | Async |
| tx_reset | I | Reset for the TX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The core handles synchronizing the tx_reset input to the appropriate clock domains within the core. | Async |
| rx_core_clk | I | The rx_core_clk signal is used to clock the receive AXI4-Stream interface. It is an input when the FIFO is included and is not an input port when in low latency mode with FIFO not included; instead it is driven internally by rx_clk_out. | rx_core_clk |