Core Overview - 2.6 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

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2.6 English

The following figure shows major functional blocks of the Timer Syncer IP. In this figure, only four instances of the port timer are shown as an example. The number of port instances are user selectable at the time of generating the core. This core supports up to 16 instances of port timers.

Figure 1. Timer Syncer IP Functional Block Diagram

The Timer Syncer IP contains all functions and interfaces needed to implement a variety of ToD topologies and applications. It can be controlled with either software or hardware devices. The System Timer maintains time on the free-running system time clock (ts_clk) and provides mechanism to synchronize the timer values with various other port timers, each of which may be clocked on their respective clocks (phy_clk).

The System Timer IP provides timer values in two formats namely, Timestamp format (or ToD format) and Correction Field (CF) format. The Timestamp format is comprised of 80 bits containing fields of unsigned positive seconds and nanoseconds such as {seconds[47:0], nanoseconds[31:0] }. The Correction Field (CF) format is a signed 64b value in nanoseconds multiplied by 2+16. Subsequent sections describe functional blocks and interfaces.