A number of issues can commonly occur during the first hardware test of an 1G/10G/25G Switching Ethernet Subsystem. These should be checked as indicated below.
It is assumed that the 1G/10G/25G Ethernet Subsystem has already passed all simulation testing which is being implemented in hardware. This is a pre-requisite for any kind of hardware debug.
The usual sequence of debugging is to proceed in the following sequence:
- Clean up signal integrity.
- Ensure that the SerDes achieves clock data recovery (CDR) lock.
- Check that the 1G/10G/25G Ethernet Subsystem IP has achieved word sync.
- Proceed to Interface and Protocol debug.