PTP System Timer Ports - 2.6 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

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2.6 English
Table 1. PTP System Timer Ports
Signal Direction Clock Domain Description
sys_tod_sec[48:0] OUT ts_clk System timer ToD seconds field
sys_tod_ns[31:0] OUT ts_clk System timer ToD nano-seconds field
sys_tod_corr[63:0] OUT ts_clk System timer ToD CF format
update_timer OUT ts_clk

Sync update pulse to the port timer blocks

Asserted when the master timer is synchronized either by the Ext ToD I/F or via register updates

sys_timer_1pps_out OUT ts_clk

1-PPS output to external ToD bus block

This port is asserted when system timer’s nano-second field rolls over