User Interface - 2.6 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)
Document ID
PG292
Release Date
2021-02-05
Version
2.6 English

General purpose I/Os (GPIOs) are provided to control the example design. The user input and output ports are described in the following table.

Table 1. User I/O Ports
Name Size I/O Description
sys_reset 1 I Reset for the core.
gt_ref_clk_p 1 I Differential input clk to GT.
gt_ref_clk_n 1 I Differential input clk to GT. This clock frequency should be equal to the GT RefClk frequency mentioned in the Vivado IDE GT Selection and Configuration tab.
dclk 1 I Stable/free running input clk to GT. This clock frequency should be equal to the GT DRP clock frequency mentioned in the Vivado IDE GT Selection and Configuration tab.
rx_gt_locked_led_0 1 O Indicates that GT has been locked.
rx_block_lock_led_0 1 O Indicates RX block lock has been achieved.
restart_tx_rx_0 1 I This signal is used to restart the packet generation and reception for the data sanity test when the packet generator and the packet monitor are in idle state.
completion_status 5 O This signal represents the test status/result.
  • 5'd0 Test did not run.
  • 5’d1 PASSED 25GE/10GE CORE TEST SUCCESSFULLY COMPLETED.
  • 5'd2 No block lock on any lanes.
  • 5'd3 Not all lanes achieved block lock.
  • 5'd4 Some lanes lost block lock after achieving block lock.
  • 5'd5 No lane sync on any lanes.
  • 5'd6 Not all lanes achieved sync.
  • 5'd7 Some lanes lost sync after achieving sync.
  • 5'd8 No alignment status or rx_status was achieved.
  • 5'd9 Loss of alignment status or rx_status after both were achieved.
  • 5'd10 TX timed out.
  • 5'd11 No TX data was sent.
  • 5'd12 Number of packets received did not equal the number of packets sent.
  • 5'd13 Total number of bytes received did not equal the total number of bytes sent.
  • 5'd14 A protocol error was detected.
  • 5'd15 Bit errors were detected in the received packets.
  • 5'd31 Test is stuck in reset.
mode_change_* 1 I This is used to switch the core speed.
core_speed_* 1 O

This signal indicates the speed with which the core is working:

  • 2'b00: 25G
  • 2'b01: 1G
  • 2'b10: 10G
  • 2'b11: Reserved
send_continuous_pkts_* 1 I This port can be used to send continuous packets for board validation.
  • 1'b0 - Sends fixed 20 packets for simulation.
  • 1'b1 - Sends continuous packets for board.
ctl_core_speed_sel 2 I This signal is used to set the operating speed of the core.
  • 2'b00 = 25G
  • 2'b01= 1G
  • 2'b01= 10G
  • 2'b11 = Reserved