| Name | Size | I/O | Description | |
|---|---|---|---|---|
| gt_loopback_in_* | 3 | I | GT loopback input signal. Refer to the GT user guide. Note: This port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
|
| gt_txp_out | 1 | O | Differential serial GT TX output Note: This port is available when the
Include GT subcore in
core option and Board support is
selected in the GT Selection and Configuration
tab.
|
|
| gt_txn_out | 1 | O | Differential serial GT TX output. Note: This port is available when the
Include GT subcore in
core option and Board support is
selected in the GT Selection and Configuration
tab.
|
|
| gt_rxn_in | 1 | I | Differential serial GT RX input. Note: This port is available when the
Include
GT subcore in core
option and Board support is selected in the GT Selection and
Configuration tab.
|
|
| gt_rxp_in | 1 | I | Differential serial GT RX input. Note: This port is available when the
Include
GT subcore in core
option and Board support is selected
|
|
| gt_rxp_in_0 | 1 | I | Differential serial GT RX input for lane 0. Note: This port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
|
| gt_rxn_in_0 | 1 | I | Differential serial GT RX input for lane 0. Note: This port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
|
| txuserrdy_out_* | 1 | O | TX user ready output signal from Core (reset Interface IP) to GT (Versal devices only). | |
| rxuserrdy_out_* | 1 | O | RX user ready output signal from Core (reset Interface IP) to GT (Versal devices only). | |
| mst_tx_reset_* | 1 | O | TX master reset output signal from Core to GT (Versal devices only). | |
| mst_rx_reset_* | 1 | O | RX master reset output signal from Core to GT (Versal devices only). | |
| mst_tx_dp_reset_* | 1 | O | TX master reset output signal from GT reset IP to the core (Versal devices only). | |
| mst_rx_dp_reset_* | 1 | O | RX master reset output signal from GT reset IP to the core (Versal devices only). | |
| mst_tx_resetdone_* | 1 | I | TX master resetdone signal from GT to Core (Versal devices only). | |
| mst_rx_resetdone_* | 1 | I | RX master resetdone signal from GT to Core (Versal devices only). | |
| gtwiz_loopback_out_* | 3 | O | GT loopback output signal from AXI4-Lite
register map (non-Versal devices only). Note: This port is available when the
Include GT subcore in example
design option is selected in the GT
Selection and Configuration tab and the AXI4-Lite interface is selected from configuration
tab.
|
|
| gtwiz_tx_rate_* | 8 | O | GT TX line rate select from the AXI4-Lite
register map (Versal devices only). See the
appropriate GT user guide. Note: This port is available
when the Include GT subcore in example
design option is selected in the GT
Selection and Configuration tab and the AXI4-Lite interface is selected from configuration
tab.
|
|
| gtwiz_rx_rate_* | 8 | O | GT RX line rate select from the AXI4-Lite
register map (Versal devices only). Note: This port is available when the
Include GT subcore in example
design option is selected in the GT
Selection and Configuration tab and the AXI4-Lite interface is selected from configuration
tab.
|
|
| gtwiz_loopback_* | 3 | O | GT loopback output signal from AXI4-Lite
register map (Versal devices only). Note: This port is available when AXI4-Lite interface is selected from the
configuration tab.
|
|
| gt_txp_out_0 | 1 | O | Differential serial GT TX output for lane
0. Note: This port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
|
| gt_txn_out_0 | 1 | O | Differential serial GT TX output for lane
0. Note: This port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|