XPM_MEMORY_SPRAM - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Parameterized Macro: Single Port RAM

  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: XPM_MEMORY
  • Families: UltraScale, UltraScale+

Introduction

This macro is used to instantiate Single Port RAM. Reads and writes to the memory can be done through Port A.

The following describes the basic read and write port usage of an XPM_MEMORY instance.
  • All synchronous signals are sensitive to the rising edge of clka, which is assumed to be a buffered and toggling clock signal behaving according to target device and memory primitive requirements.
  • A read operation is implicitly performed to address addra combinatorially. The data output is registered each clka cycle that ena is asserted.
  • Read data appears on the douta port READ_LATENCY_A clka cycles after the associated read operation.
  • A write operation is explicitly performed, writing dina to address addra, when both ena and wea are asserted on each clka cycle.
  • All read and write operations are gated by the value of ena on the initiating clka cycle, regardless of input or output latencies. The addra and wea inputs have no effect when ena is de-asserted on the coincident clka cycle.
  • The behavior of douta with respect to the combination of dina and addra is a function of WRITE_MODE_A.
  • For each clka cycle that rsta is asserted, the final output register is immediately but synchronously reset to READ_RESET_VALUE_A, irrespective of READ_LATENCY_A.
  • For each clka cycle that regcea is asserted and rsta is de-asserted, the final output register captures and outputs the value from the previous pipeline register.
  • Undriven or unknown values provided on module inputs will produce undefined memory array and output port behavior.
  • When MEMORY INIT PARAM is used, the maximum supported memory size 4K bits.
  • Memory initialization with Asymmetric Byte Write Enable is not supported.
  • For better timing performance in larger memories (>1 Mb), use CASCADE_HEIGHT of 1 with sufficient read latencies.
  • Choosing the Invalid Configuration will result in a DRC error.
Note: Writing to an out-of-range address location may overwrite a valid address location when effective address bits match to a physical memory address location.
  • The use of UltraRAM’s dedicated input and output registers are controlled by synthesis based on the READ_LATENCY_B value. For example, if 4 UltraRAMs are in cascade and the READ_LATENCY_B is ≥ 4, then synthesis will absorb as much registers inside UltraRAM primitive as possible.

  • For UltraRAM's, OREG enabled when READ_LATENCY_B >= 3 in all write modes.
  • For larger memories (≥2 MB), the recommended read latency must be > 8 because the default cascade height used by Vivado synthesis is 8.

Timing Diagrams





Note: The UltraRAM primitive does not support Write/Read access in the clock cycle just before assertion of sleep gets recognized on the positive edge of the clock when its OREG attribute is set to TRUE. For UltraRAM configurations, Write/Read access to the memory is not allowed in the clock cycle just before the assertion of sleep.

ECC Modes

Only the UltraRAM primitives support ECC when the memory type is set to Single Port RAM. The three ECC modes supported are:

  • Both encode and decode
  • Encode only
  • Decode only

The read and write usage of the three ECC Modes are the same as described in the Introduction section above. See the “Built-in Error Correction” section of the UltraScale Architecture Memory Resources User Guide (UG573) for more details on this feature like Error Injection and syndrome bits calculations.

There are restrictions on the attributes WRITE_DATA_WIDTH_A, READ_DATA_WIDTH_A, and MEMORY_SIZE in each of the above ECC modes.

  • Both encode and decode WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_A must be multiples of 64-bits. Violating this rule will results in a DRC in XPM_Memory.
  • Encode only WRITE_DATA_WIDTH_A must be a multiple of 64 bits and READ_DATA_WIDTH_A must be a multiple of 72-bits. MEMORY_SIZE must be a multiple of READ_DATA_WIDTH_A. Violating these rules will result in a DRC.
  • Decode only WRITE_DATA_WIDTH_A must be a multiple of 72 bits and READ_DATA_WIDTH_A must be a multiple of 64-bits. MEMORY_SIZE must be a multiple of WRITE_DATA_WIDTH_A. Violating these rules will result in a DRC.

When ECC is enabled the following are not supported:

  • Asymmetry
  • Initialization
  • Reset (neither non-zero reset value nor reset assertion)
Note: ECC uses a hard-ECC block available in the BRAM/URAM macro and the data width should be multiples of 64/72. Use ECC IP for other data width combinations.

Auto Sleep Mode

  • This feature is applicable only when MEMORY_PRIMITIVE is URAM and is controlled internally in the UltraRAM to check if it can be put in sleep mode and when it needs to wake up. Thus power savings are obtained automatically without having to explicitly control the SLEEP Pin.
  • When AUTO_SLEEP_TIME is 0, the feature is disabled. When AUTO_SLEEP_TIME is non-zero, XPM_MEMORY constructs the pipeline registers equal to AUTO_SLEEP_TIME value on all input signals except rst[a|b].
  • If AUTO_SLEEP_TIME is too low, then UltraRAM goes into sleep and wakeup too often, which can cause more power to be consumed.
  • The number of sleep cycles achieved is calculated by following formula:
    • If number of consecutive inactive cycles is <AUTO_SLEEP_TIME, then number of sleep cycles = 0.
    • If number of consecutive inactive cycles is ≥AUTO_SLEEP_TIME, Then number of consecutive sleep cycles = Number of consecutive inactive cycles – 3.
    • Inactive cycle is defined as a cycle where there is no Read/Write operation from either port.
  • The latency between the read operation and the data arrival at dout[a|b] is AUTO_SLEEP_TIME + READ_LATENCY_[A|B] clock cycles (Assuming that REGCE is high when the output data pipe line exists).
  • When the READ_LATENCY_[A|B] is set to 1 or 2, XPM_Memory behaviorally models the AUTO SLEEP feature and forces ‘x’ on DOUT[A|B] when the RAM is in Auto Sleep Mode. For READ_LATENCY_[A|B] greater than 2, the propagation of ‘x’ cannot happen to the DOUT[A|B] as the output registers gets the clock enable (delayed read enable) after UltraRAM comes out of sleep mode.
  • The Auto Sleep mode is most effective for larger memory sizes or any memory with very little activity.
Timing diagrams for Auto Sleep Mode at various read latencies are shown below.

Port Descriptions

Port Direction Width Domain Sense Handling if Unused Function
addra Input ADDR_WIDTH_A clka NA Active Address for port A write and read operations.
clka Input 1 NA EDGE_RISING Active Clock signal for port A.
dbiterra Output 1 clka LEVEL_HIGH DoNotCare Status signal to indicate double bit error occurrence on the data output of port A.
dina Input WRITE_DATA_WIDTH_A clka NA Active Data input for port A write operations.
douta Output READ_DATA_WIDTH_A clka NA Active Data output for port A read operations.
ena Input 1 clka LEVEL_HIGH Active

Memory enable signal for port A.

Must be high on clock cycles when read or write operations are initiated. Pipelined internally.

injectdbiterra Input 1 clka LEVEL_HIGH 0 Controls double bit error injection on input data when ECC enabled (Error injection capability is not available in "decode_only" mode).
injectsbiterra Input 1 clka LEVEL_HIGH 0 Controls single bit error injection on input data when ECC enabled (Error injection capability is not available in "decode_only" mode).
regcea Input 1 clka LEVEL_HIGH 1 Clock Enable for the last register stage on the output data path.
rsta Input 1 clka LEVEL_HIGH Active Reset signal for the final port A output register stage. Synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A.
sbiterra Output 1 clka LEVEL_HIGH DoNotCare Status signal to indicate single bit error occurrence on the data output of port A.
sleep Input 1 NA LEVEL_HIGH 0 sleep signal to enable the dynamic power saving feature.
wea Input WRITE_DATA_WIDTH_A / BYTE_WRITE_WIDTH_A clka LEVEL_HIGH Active

Write enable vector for port A input data port dina. 1 bit wide when word-wide writes are used.

In byte-wide write configurations, each bit controls the writing one byte of dina to address addra. For example, to synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A is 32, wea would be 4'b0010.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
ADDR_WIDTH_A DECIMAL 1 to 20 6

Specify the width of the port A address port addra, in bits.

Must be large enough to access the entire memory from port A, i.e. >= $clog2(MEMORY_SIZE/[WRITE|READ]_DATA_WIDTH_A).

AUTO_SLEEP_TIME DECIMAL 0 to 15 0

Specify the number of clka cycles to auto-sleep, if feature is available in architecture.

  • 0 - Disable auto-sleep feature
  • 3-15 - Number of auto-sleep latency cycles

Do not change from the value provided in the template instantiation.

BYTE_WRITE_WIDTH_A DECIMAL 1 to 4608 32

To enable byte-wide writes on port A, specify the byte width, in bits.

  • 8- 8-bit byte-wide writes, legal when WRITE_DATA_WIDTH_A is an integer multiple of 8
  • 9- 9-bit byte-wide writes, legal when WRITE_DATA_WIDTH_A is an integer multiple of 9

Or to enable word-wide writes on port A, specify the same value as for WRITE_DATA_WIDTH_A.

CASCADE_HEIGHT DECIMAL 0 to 64 0

0- No Cascade Height, Allow Vivado Synthesis to choose.

1 or more - Vivado Synthesis sets the specified value as Cascade Height.

ECC_BIT_RANGE STRING String "7:0"

This parameter is only used by synthesis. Specify the ECC bit range on the provided data.

"7:0" - it specifies lower 8 bits are ECC bits.

ECC_MODE STRING "no_ecc", "both_encode_and_decode", "decode_only", "encode_only" "no_ecc"
  • "no_ecc" - Disables ECC
  • "encode_only" - Enables ECC Encoder only
  • "decode_only" - Enables ECC Decoder only
  • "both_encode_and_decode" - Enables both ECC Encoder and Decoder
ECC_TYPE STRING "none", "ECCHSIAO32-7", "ECCHSIAO64-8", "ECCHSIAO128-9", "ECCH32-7", "ECCH64-8" "none"

This parameter is only used by synthesis. Specify the algorithm used to generate the ecc bits outside the XPM Memory.

XPM Memory does not performs ECC operation with this parameter.

  • "none" - No ECC
  • "ECCH32-7" - 32 bit ECC Hamming algorithm is used
  • "ECCH64-8" - 64 bit ECC Hamming algorithm is used
  • "ECCHSIAO32-7" - 32 bit ECC HSIAO algorithm is used
  • "ECCHSIAO64-8" - 64 bit ECC HSIAO algorithm is used
  • "ECCHSIAO128-9" - 128 bit ECC HSIAO algorithm is used
IGNORE_INIT_SYNTH DECIMAL 0 to 1 0

0 - Initiazation file if specified will applies for both simulation and synthesis

1 - Initiazation file if specified will applies for only simulation and will ignore for synthesis

MEMORY_INIT_FILE STRING String "none"

Specify "none" (including quotes) for no memory initialization, or specify the name of a memory initialization file- Enter only the name of the file with .mem extension, including quotes but without path (e.g. "my_file.mem").

File format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. Initialization of memory happens through the file name specified only when parameter MEMORY_INIT_PARAM value is equal to "".

When using XPM_MEMORY in a project, add the specified file to the Vivado project as a design source.

MEMORY_INIT_PARAM STRING String "0"

Specify "" or "0" (including quotes) for no memory initialization through parameter, or specify the string containing the hex characters. Enter only hex characters with each location separated by delimiter (,).

Parameter format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory.

For example, if the narrowest data width is 8, and the depth of memory is 8 locations, then the parameter value should be passed as shown below.

parameter MEMORY_INIT_PARAM = "AB,CD,EF,1,2,34,56,78"

Where "AB" is the 0th location and "78" is the 7th location.

MEMORY_OPTIMIZATION STRING "true", "false" "true" Specify "true" to enable the optimization of unused memory or bits in the memory structure. Specify "false" to disable the optimization of unused memory or bits in the memory structure
MEMORY_PRIMITIVE STRING "auto", "block", "distributed", "mixed", "ultra" "auto"

Designate the memory primitive (resource type) to use.

  • "auto"- Allow Vivado Synthesis to choose
  • "distributed"- Distributed memory
  • "block"- Block memory
  • "ultra"- Ultra RAM memory
  • "mixed"- Mixed memory
NOTE: There may be a behavior mismatch if Block RAM or Ultra RAM specific features, like ECC or Asymmetry, are selected with MEMORY_PRIMITIVE set to "auto".
MEMORY_SIZE DECIMAL 2 to 150994944 2048 Specify the total memory array size, in bits. For example, enter 65536 for a 2kx32 RAM.
  • When ECC is enabled and set to "encode_only", then the memory size has to be multiples of READ_DATA_WIDTH_A
  • When ECC is enabled and set to "decode_only", then the memory size has to be multiples of WRITE_DATA_WIDTH_A
MESSAGE_CONTROL DECIMAL 0 to 1 0 Specify 1 to enable the dynamic message reporting such as collision warnings, and 0 to disable the message reporting
RAM_DECOMP STRING "auto", "area", "power" "auto"

Specifies the decomposition of the memory.

"auto" - Synthesis selects default.

"power" - Synthesis selects a strategy to reduce switching activity of RAMs and maps using widest configuration possible.

"area" - Synthesis selects a strategy to reduce RAM resource count.

READ_DATA_WIDTH_A DECIMAL 1 to 4608 32

Specify the width of the port A read data output port douta, in bits. The values of READ_DATA_WIDTH_A and WRITE_DATA_WIDTH_A must be equal.

When ECC is enabled and set to "encode_only", then READ_DATA_WIDTH_A has to be multiples of 72-bits.

When ECC is enabled and set to "decode_only" or "both_encode_and_decode", then READ_DATA_WIDTH_A has to be multiples of 64-bits.

READ_LATENCY_A DECIMAL 0 to 100 2

Specify the number of register stages in the port A read data pipeline. Read data output to port douta takes this number of clka cycles.

  • To target block memory, a value of 1 or larger is required- 1 causes use of memory latch only; 2 causes use of output register.
  • To target distributed memory, a value of 0 or larger is required- 0 indicates combinatorial output.
  • Values larger than 2 synthesize additional flip-flops that are not retimed into memory primitives.
READ_RESET_VALUE_A STRING String "0"

Specify the reset value of the port A final output register stage in response to rsta input port is assertion. Since this parameter is a string, you must specify the hex values inside double quotes. For example, If the read data width is 8, then specify READ_RESET_VALUE_A = "EA";

When ECC is enabled, then reset value is not supported.

RST_MODE_A STRING "SYNC", "ASYNC" "SYNC"

Describes the behaviour of the reset

  • "SYNC" - when reset is applied, synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A
  • "ASYNC" - when reset is applied, asynchronously resets output port douta to zero
SIM_ASSERT_CHK DECIMAL 0 to 1 0

0- Disable simulation message reporting. Messages related to potential misuse will not be reported.

1- Enable simulation message reporting. Messages related to potential misuse will be reported.

USE_MEM_INIT DECIMAL 0 to 1 1

Specify 1 to enable the generation of below message and 0 to disable generation of the following message completely.

"INFO - MEMORY_INIT_FILE and MEMORY_INIT_PARAM together specifies no memory initialization. Initial memory contents will be all 0s." NOTE: This message gets generated only when there is no Memory Initialization specified either through file or Parameter.
USE_MEM_INIT_MMI DECIMAL 0 to 1 0

Specify 1 to expose this memory information to be written out in the MMI file.

WAKEUP_TIME STRING "disable_sleep", "use_sleep_pin" "disable_sleep" Specify "disable_sleep" to disable dynamic power saving option, and specify "use_sleep_pin" to enable the dynamic power saving option
WRITE_DATA_WIDTH_A DECIMAL 1 to 4608 32

Specify the width of the port A write data input port dina, in bits. The values of WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_A must be equal.

When ECC is enabled and set to "encode_only" or "both_encode_and_decode", then WRITE_DATA_WIDTH_A must be multiples of 64-bits.

When ECC is enabled and set to "decode_only", then WRITE_DATA_WIDTH_A must be multiples of 72-bits.

WRITE_MODE_A STRING "read_first", "no_change", "write_first" "read_first" Write mode behavior for port A output data port, douta.
WRITE_PROTECT DECIMAL 0 to 1 1

Default value is 1, means write is protected through enable and write enable and hence the LUT is placed before the memory. This is the default behaviour to access memory.

When 0, disables write protection. Write enable (WE) directly connected to memory.

NOTE: Disable this option only if the advanced users can guarantee that the write enable (WE) cannot be given without enable (EN).

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library xpm;
use xpm.vcomponents.all;

-- xpm_memory_spram: Single Port RAM
-- Xilinx Parameterized Macro, version 2024.1

xpm_memory_spram_inst : xpm_memory_spram
generic map (
   ADDR_WIDTH_A => 6,              -- DECIMAL
   AUTO_SLEEP_TIME => 0,           -- DECIMAL
   BYTE_WRITE_WIDTH_A => 32,       -- DECIMAL
   CASCADE_HEIGHT => 0,            -- DECIMAL
   ECC_BIT_RANGE => "7:0",         -- String
   ECC_MODE => "no_ecc",           -- String
   ECC_TYPE => "none",             -- String
   IGNORE_INIT_SYNTH => 0,         -- DECIMAL
   MEMORY_INIT_FILE => "none",     -- String
   MEMORY_INIT_PARAM => "0",       -- String
   MEMORY_OPTIMIZATION => "true",  -- String
   MEMORY_PRIMITIVE => "auto",     -- String
   MEMORY_SIZE => 2048,            -- DECIMAL
   MESSAGE_CONTROL => 0,           -- DECIMAL
   RAM_DECOMP => "auto",           -- String
   READ_DATA_WIDTH_A => 32,        -- DECIMAL
   READ_LATENCY_A => 2,            -- DECIMAL
   READ_RESET_VALUE_A => "0",      -- String
   RST_MODE_A => "SYNC",           -- String
   SIM_ASSERT_CHK => 0,            -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   USE_MEM_INIT => 1,              -- DECIMAL
   USE_MEM_INIT_MMI => 0,          -- DECIMAL
   WAKEUP_TIME => "disable_sleep", -- String
   WRITE_DATA_WIDTH_A => 32,       -- DECIMAL
   WRITE_MODE_A => "read_first",   -- String
   WRITE_PROTECT => 1              -- DECIMAL
)
port map (
   dbiterra => dbiterra,             -- 1-bit output: Status signal to indicate double bit error occurrence
                                     -- on the data output of port A.

   douta => douta,                   -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
   sbiterra => sbiterra,             -- 1-bit output: Status signal to indicate single bit error occurrence
                                     -- on the data output of port A.

   addra => addra,                   -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
   clka => clka,                     -- 1-bit input: Clock signal for port A.
   dina => dina,                     -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
   ena => ena,                       -- 1-bit input: Memory enable signal for port A. Must be high on clock
                                     -- cycles when read or write operations are initiated. Pipelined
                                     -- internally.

   injectdbiterra => injectdbiterra, -- 1-bit input: Controls double bit error injection on input data when
                                     -- ECC enabled (Error injection capability is not available in
                                     -- "decode_only" mode).

   injectsbiterra => injectsbiterra, -- 1-bit input: Controls single bit error injection on input data when
                                     -- ECC enabled (Error injection capability is not available in
                                     -- "decode_only" mode).

   regcea => regcea,                 -- 1-bit input: Clock Enable for the last register stage on the output
                                     -- data path.

   rsta => rsta,                     -- 1-bit input: Reset signal for the final port A output register
                                     -- stage. Synchronously resets output port douta to the value specified
                                     -- by parameter READ_RESET_VALUE_A.

   sleep => sleep,                   -- 1-bit input: sleep signal to enable the dynamic power saving feature.
   wea => wea                        -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                                     -- for port A input data port dina. 1 bit wide when word-wide writes
                                     -- are used. In byte-wide write configurations, each bit controls the
                                     -- writing one byte of dina to address addra. For example, to
                                     -- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                     -- is 32, wea would be 4'b0010.

);

-- End of xpm_memory_spram_inst instantiation

Verilog Instantiation Template


// xpm_memory_spram: Single Port RAM
// Xilinx Parameterized Macro, version 2024.1

xpm_memory_spram #(
   .ADDR_WIDTH_A(6),              // DECIMAL
   .AUTO_SLEEP_TIME(0),           // DECIMAL
   .BYTE_WRITE_WIDTH_A(32),       // DECIMAL
   .CASCADE_HEIGHT(0),            // DECIMAL
   .ECC_BIT_RANGE("7:0"),         // String
   .ECC_MODE("no_ecc"),           // String
   .ECC_TYPE("none"),             // String
   .IGNORE_INIT_SYNTH(0),         // DECIMAL
   .MEMORY_INIT_FILE("none"),     // String
   .MEMORY_INIT_PARAM("0"),       // String
   .MEMORY_OPTIMIZATION("true"),  // String
   .MEMORY_PRIMITIVE("auto"),     // String
   .MEMORY_SIZE(2048),            // DECIMAL
   .MESSAGE_CONTROL(0),           // DECIMAL
   .RAM_DECOMP("auto"),           // String
   .READ_DATA_WIDTH_A(32),        // DECIMAL
   .READ_LATENCY_A(2),            // DECIMAL
   .READ_RESET_VALUE_A("0"),      // String
   .RST_MODE_A("SYNC"),           // String
   .SIM_ASSERT_CHK(0),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   .USE_MEM_INIT(1),              // DECIMAL
   .USE_MEM_INIT_MMI(0),          // DECIMAL
   .WAKEUP_TIME("disable_sleep"), // String
   .WRITE_DATA_WIDTH_A(32),       // DECIMAL
   .WRITE_MODE_A("read_first"),   // String
   .WRITE_PROTECT(1)              // DECIMAL
)
xpm_memory_spram_inst (
   .dbiterra(dbiterra),             // 1-bit output: Status signal to indicate double bit error occurrence
                                    // on the data output of port A.

   .douta(douta),                   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
   .sbiterra(sbiterra),             // 1-bit output: Status signal to indicate single bit error occurrence
                                    // on the data output of port A.

   .addra(addra),                   // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
   .clka(clka),                     // 1-bit input: Clock signal for port A.
   .dina(dina),                     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
   .ena(ena),                       // 1-bit input: Memory enable signal for port A. Must be high on clock
                                    // cycles when read or write operations are initiated. Pipelined
                                    // internally.

   .injectdbiterra(injectdbiterra), // 1-bit input: Controls double bit error injection on input data when
                                    // ECC enabled (Error injection capability is not available in
                                    // "decode_only" mode).

   .injectsbiterra(injectsbiterra), // 1-bit input: Controls single bit error injection on input data when
                                    // ECC enabled (Error injection capability is not available in
                                    // "decode_only" mode).

   .regcea(regcea),                 // 1-bit input: Clock Enable for the last register stage on the output
                                    // data path.

   .rsta(rsta),                     // 1-bit input: Reset signal for the final port A output register stage.
                                    // Synchronously resets output port douta to the value specified by
                                    // parameter READ_RESET_VALUE_A.

   .sleep(sleep),                   // 1-bit input: sleep signal to enable the dynamic power saving feature.
   .wea(wea)                        // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                                    // for port A input data port dina. 1 bit wide when word-wide writes are
                                    // used. In byte-wide write configurations, each bit controls the
                                    // writing one byte of dina to address addra. For example, to
                                    // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                    // is 32, wea would be 4'b0010.

);

// End of xpm_memory_spram_inst instantiation