EFUSE_USR - 2023.2 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-10-18
Version
2023.2 English

Primitive: 32-bit non-volatile design ID

  • PRIMITIVE_GROUP: CONFIGURATION
  • PRIMITIVE_SUBGROUP: EFUSE
  • Families: UltraScale FPGAs, UltraScale+ FPGAs

Introduction

Provides internal access to the 32 non-volatile, user-programmable eFUSE bits.

Port Descriptions

Port Direction Width Function
EFUSEUSR<31:0> Output 32 User eFUSE register value output.

Design Entry Method

Instantiation Recommended
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
SIM_EFUSE_VALUE HEX Any 32-bit HEX value All zeroes Value of the 32-bit non-volatile value used in simulation.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- EFUSE_USR: 32-bit non-volatile design ID
--            UltraScale
-- Xilinx HDL Language Template, version 2023.2

EFUSE_USR_inst : EFUSE_USR
generic map (
   SIM_EFUSE_VALUE => X"00000000"  -- Value of the 32-bit non-volatile value used in simulation.
)
port map (
   EFUSEUSR => EFUSEUSR  -- 32-bit output: User eFUSE register value output.
);

-- End of EFUSE_USR_inst instantiation

Verilog Instantiation Template


// EFUSE_USR: 32-bit non-volatile design ID
//            UltraScale
// Xilinx HDL Language Template, version 2023.2

EFUSE_USR #(
   .SIM_EFUSE_VALUE(32'h00000000)  // Value of the 32-bit non-volatile value used in simulation.
)
EFUSE_USR_inst (
   .EFUSEUSR(EFUSEUSR)  // 32-bit output: User eFUSE register value output.
);

// End of EFUSE_USR_inst instantiation

Related Information

  • UltraScale Architecture Configuration User Guide (UG570)