USR_ACCESSE2 - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Primitive: Configuration Data Access

  • PRIMITIVE_GROUP: CONFIGURATION
  • PRIMITIVE_SUBGROUP: USR_ACCESS
  • Families: UltraScale, UltraScale+

Introduction

The USR_ACCESSE2 design element enables access to the 32-bit AXSS register within the configuration logic. This enables device logic to access static data that can be set from the bitstream. The primitive and functionality for the Kintex UltraScale and Virtex UltraScale FPGAs are identical to that for the 7 series.

The USR_ACCESSE2 register AXSS can be used to provide a single 32-bit constant value to the device logic. The register contents can be defined during bitstream generation, avoiding the need to recompile the design as would be required if distributed RAM was used to hold the constant. A constant can be used to track the version of the design, or any other information you require.

Port Descriptions

Port Direction Width Function
CCLK Internal 1 Internal clock pin for timing. UltraScale+ only
CFGCLK Output 1 Configuration Clock.
DATA<31:0> Output 32 Configuration Data reflecting the contents of the AXSS register.
DATAVALID Output 1 Active-High Data Valid.

Design Entry Method

Instantiation Recommended
Inference No
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- USR_ACCESSE2: Configuration Data Access
--               UltraScale
-- Xilinx HDL Language Template, version 2024.1

USR_ACCESSE2_inst : USR_ACCESSE2
port map (
   CFGCLK => CFGCLK,       -- 1-bit output: Configuration Clock
   DATA => DATA,           -- 32-bit output: Configuration Data reflecting the contents of the AXSS register
   DATAVALID => DATAVALID  -- 1-bit output: Active-High Data Valid
);

-- End of USR_ACCESSE2_inst instantiation

Verilog Instantiation Template


// USR_ACCESSE2: Configuration Data Access
//               UltraScale
// Xilinx HDL Language Template, version 2024.1

USR_ACCESSE2 USR_ACCESSE2_inst (
   .CFGCLK(CFGCLK),       // 1-bit output: Configuration Clock
   .DATA(DATA),           // 32-bit output: Configuration Data reflecting the contents of the AXSS register
   .DATAVALID(DATAVALID)  // 1-bit output: Active-High Data Valid
);

// End of USR_ACCESSE2_inst instantiation

Related Information

  • UltraScale Architecture Configuration User Guide (UG570)