HARD_SYNC - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Primitive: Metastability Hardened Registers

  • PRIMITIVE_GROUP: REGISTER
  • PRIMITIVE_SUBGROUP: METASTABILITY
  • Families: UltraScale, UltraScale+

Introduction

Metastability hardened registers are generally used for asynchronous domain crossings to synchronize signals, which can incur set up or hold time violations. The LATENCY attribute can be set to configure a dual or triple register synchronizer configuration. The HARD_SYNC must be manually placed using the XDC LOC constraint.

Port Descriptions

Port Direction Width Function
CLK Input 1 Clock input
DIN Input 1 Data input
DOUT Output 1 Data output

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT BINARY 1'b0, 1'b1 1'b0 Specifies the initial values of the HARD_SYNC output upon completion of configuration and release of GSR.
IS_CLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies to use the programmable inversion on the CLK input to change the clock from active-High to active-Low.
LATENCY DECIMAL 2, 3 2 Specifies whether to use a two stage or three stage synchronizer. Three stage will exhibit better MTBF characteristics however have an additional clock cycle of latency.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- HARD_SYNC: Metastability Hardened Registers
--            UltraScale
-- Xilinx HDL Language Template, version 2024.1

HARD_SYNC_inst : HARD_SYNC
generic map (
   INIT => '0',            -- Initial values, '0', '1'
   IS_CLK_INVERTED => '0', -- Programmable inversion on CLK input
   LATENCY => 2            -- 2-3
)
port map (
   DOUT => DOUT, -- 1-bit output: Data
   CLK => CLK,   -- 1-bit input: Clock
   DIN => DIN    -- 1-bit input: Data
);

-- End of HARD_SYNC_inst instantiation

Verilog Instantiation Template


// HARD_SYNC: Metastability Hardened Registers
//            UltraScale
// Xilinx HDL Language Template, version 2024.1

HARD_SYNC #(
   .INIT(1'b0),            // Initial values, 1'b0, 1'b1
   .IS_CLK_INVERTED(1'b0), // Programmable inversion on CLK input
   .LATENCY(2)             // 2-3
)
HARD_SYNC_inst (
   .DOUT(DOUT), // 1-bit output: Data
   .CLK(CLK),   // 1-bit input: Clock
   .DIN(DIN)    // 1-bit input: Data
);

// End of HARD_SYNC_inst instantiation

Related Information

  • UltraScale Architecture Configurable Logic Block User Guide (UG574)