LDCE - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Primitive: Transparent Latch with Clock Enable and Asynchronous Clear

  • PRIMITIVE_GROUP: REGISTER
  • PRIMITIVE_SUBGROUP: LATCH
  • Families: UltraScale, UltraScale+

Introduction

This design element is a transparent data latch with asynchronous clear and gate enable. When the asynchronous clear input (CLR) is active, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D) input while the gate (G) input and gate enable (GE) are active and CLR is not active. If (GE) is Low, data on (D) cannot be latched. The data on the (D) input during the gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as (G) or (GE) remains Low.

This latch is asynchronously initialized when power is applied. When global set/reset (GSR) is active upon power-up or when GSR is asserted via the STARTUP block, the value of the INIT attribute is placed on the latch's output.

Logic Table

Inputs Outputs
CLR GE G D Q
1 X X X 0
0 0 X X No Change
0 1 1 D D
0 1 0 X No Change
0 1 D D

Port Descriptions

Port Direction Width Function
CLR Input 1 Asynchronous clear. Polarity is determined by the IS_CLR_INVERTED attribute.
D Input 1 Data input
G Input 1 Gate input. Polarity is determined by the IS_G_INVERTED attribute.
GE Input 1 Active-High latch gate enable.
Q Output 1 Data output.

Design Entry Method

Instantiation Yes
Inference Yes
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT BINARY 1'b0, 1'b1 1'b0 Sets the initial value of Q output after configuration or when GSR is asserted.
Programmable Inversion Attributes: Specifies whether or not to use the optional inversion on specific pins of this component to change the active polarity of the pin function. When set to 1 on a gate pin (G), it creates an active-Low latch. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity.
IS_CLR_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion for the CLR pin of this component.
IS_G_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion for the G pin of this component.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- LDCE: Transparent Latch with Clock Enable and Asynchronous Clear
--       UltraScale
-- Xilinx HDL Language Template, version 2024.1

LDCE_inst : LDCE
generic map (
   INIT => '0',            -- Initial value of latch, '0', '1'
   -- Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
   IS_CLR_INVERTED => '0', -- Optional inversion for CLR
   IS_G_INVERTED => '0'    -- Optional inversion for G
)
port map (
   Q => Q,     -- 1-bit output: Data
   CLR => CLR, -- 1-bit input: Asynchronous clear
   D => D,     -- 1-bit input: Data
   G => G,     -- 1-bit input: Gate
   GE => GE    -- 1-bit input: Gate enable
);

-- End of LDCE_inst instantiation

Verilog Instantiation Template


// LDCE: Transparent Latch with Clock Enable and Asynchronous Clear
//       UltraScale
// Xilinx HDL Language Template, version 2024.1

LDCE #(
   .INIT(1'b0),            // Initial value of latch, 1'b0, 1'b1
   // Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
   .IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
   .IS_G_INVERTED(1'b0)    // Optional inversion for G
)
LDCE_inst (
   .Q(Q),     // 1-bit output: Data
   .CLR(CLR), // 1-bit input: Asynchronous clear
   .D(D),     // 1-bit input: Data
   .G(G),     // 1-bit input: Gate
   .GE(GE)    // 1-bit input: Gate enable
);

// End of LDCE_inst instantiation

Related Information