XPM_CDC_PULSE - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Parameterized Macro: Pulse Transfer

  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: XPM_CDC
  • Families: UltraScale, UltraScale+

Introduction

This macro synchronizes a pulse in the source clock domain to the destination clock domain. A pulse of any size in the source clock domain, if initiated correctly, will generate a pulse the size of a single destination clock period.

For proper operation, the input data must be sampled two or more times by the destination clock. You can define the number of register stages used in the synchronizers. An optional source and destination reset may be used to reset the pulse transfer logic. You can also enable a simulation feature to generate messages which report any potential misuse of the macro.

The implementation of this macro requires some feedback logic. When simulating the macro without the optional reset signals, the input pulse signal (src_pulse) must always be defined because there is no reset logic to recover from an undefined or ‘x’ propagating through the macro.

This macro also requires the following minimum gap between subsequent pulse inputs:
2*(larger(src_clk period, dest_clk period))
The minimum gap is measured between the falling edge of a src_pulse to the rising edge of the next src_pulse. This minimum gap will guarantee that each rising edge of src_pulse will generate a pulse the size of one dest_clk period in the destination clock domain.
When using the optional reset signals, src_rst and dest_rst must be asserted simultaneously for at least the following duration to fully reset all the logic in the macro:
((DEST_SYNC_FF+2)*dest_clk_period) + (2*src_clk_period)
When reset is asserted, the input pulse signal should not toggle and the output pulse signal is not valid and should be ignored.

The following waveform demonstrates how to reset the macro and transfer back-to-back pulses while abiding the minimum gap between each pulse.

Figure 1. Timing for Macro and Transfer Back-to-Back Pulses

Port Descriptions

Port Direction Width Domain Sense Handling if Unused Function
dest_clk Input 1 NA EDGE_RISING Active Destination clock.
dest_pulse Output 1 dest_clk LEVEL_HIGH Active Outputs a pulse the size of one dest_clk period when a pulse transfer is correctly initiated on src_pulse input. This output is combinatorial unless REG_OUTPUT is set to 1.
dest_rst Input 1 dest_clk LEVEL_HIGH 0

Unused when RST_USED = 0. Destination reset signal if RST_USED = 1.

Resets all logic in destination clock domain. To fully reset the macro, src_rst and dest_rst must be asserted simultaneously for at least ((DEST_SYNC_FF+2)*dest_clk_period) + (2*src_clk_period).

src_clk Input 1 NA EDGE_RISING Active Source clock.
src_pulse Input 1 src_clk EDGE_RISING Active

Rising edge of this signal initiates a pulse transfer to the destination clock domain.

The minimum gap between each pulse transfer must be at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured between the falling edge of a src_pulse to the rising edge of the next src_pulse. This minimum gap will guarantee that each rising edge of src_pulse will generate a pulse the size of one dest_clk period in the destination clock domain.

When RST_USED = 1, pulse transfers will not be guaranteed while src_rst and/or dest_rst are asserted.

src_rst Input 1 src_clk LEVEL_HIGH 0

Unused when RST_USED = 0. Source reset signal if RST_USED = 1.

Resets all logic in source clock domain.

To fully reset the macro, src_rst and dest_rst must be asserted simultaneously for at least ((DEST_SYNC_FF+2)*dest_clk_period) + (2*src_clk_period).

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
DEST_SYNC_FF DECIMAL 2 to 10 4 Number of register stages used to synchronize signal in the destination clock domain.
INIT_SYNC_FF DECIMAL 0, 1 0

0- Disable behavioral simulation initialization value(s) on synchronization registers.

1- Enable behavioral simulation initialization value(s) on synchronization registers.

REG_OUTPUT DECIMAL 0, 1 0

0- Disable registered output

1- Enable registered output

RST_USED DECIMAL 1, 0 1

0 - No resets implemented.

1 - Resets implemented.

When RST_USED = 0, src_pulse input must always be defined during simulation since there is no reset logic to recover from an x-propagating through the macro.

SIM_ASSERT_CHK DECIMAL 0, 1 0

0- Disable simulation message reporting. Messages related to potential misuse will not be reported.

1- Enable simulation message reporting. Messages related to potential misuse will be reported.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library xpm;
use xpm.vcomponents.all;

-- xpm_cdc_pulse: Pulse Transfer
-- Xilinx Parameterized Macro, version 2024.1

xpm_cdc_pulse_inst : xpm_cdc_pulse
generic map (
   DEST_SYNC_FF => 4,   -- DECIMAL; range: 2-10
   INIT_SYNC_FF => 0,   -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
   REG_OUTPUT => 0,     -- DECIMAL; 0=disable registered output, 1=enable registered output
   RST_USED => 1,       -- DECIMAL; 0=no reset, 1=implement reset
   SIM_ASSERT_CHK => 0  -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
)
port map (
   dest_pulse => dest_pulse, -- 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
                             -- transfer is correctly initiated on src_pulse input. This output is
                             -- combinatorial unless REG_OUTPUT is set to 1.

   dest_clk => dest_clk,     -- 1-bit input: Destination clock.
   dest_rst => dest_rst,     -- 1-bit input: optional; required when RST_USED = 1
   src_clk => src_clk,       -- 1-bit input: Source clock.
   src_pulse => src_pulse,   -- 1-bit input: Rising edge of this signal initiates a pulse transfer to the
                             -- destination clock domain. The minimum gap between each pulse transfer must
                             -- be at the minimum 2*(larger(src_clk period, dest_clk period)). This is
                             -- measured between the falling edge of a src_pulse to the rising edge of the
                             -- next src_pulse. This minimum gap will guarantee that each rising edge of
                             -- src_pulse will generate a pulse the size of one dest_clk period in the
                             -- destination clock domain. When RST_USED = 1, pulse transfers will not be
                             -- guaranteed while src_rst and/or dest_rst are asserted.

   src_rst => src_rst        -- 1-bit input: optional; required when RST_USED = 1
);

-- End of xpm_cdc_pulse_inst instantiation

Verilog Instantiation Template


// xpm_cdc_pulse: Pulse Transfer
// Xilinx Parameterized Macro, version 2024.1

xpm_cdc_pulse #(
   .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
   .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
   .REG_OUTPUT(0),     // DECIMAL; 0=disable registered output, 1=enable registered output
   .RST_USED(1),       // DECIMAL; 0=no reset, 1=implement reset
   .SIM_ASSERT_CHK(0)  // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
)
xpm_cdc_pulse_inst (
   .dest_pulse(dest_pulse), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
                            // transfer is correctly initiated on src_pulse input. This output is
                            // combinatorial unless REG_OUTPUT is set to 1.

   .dest_clk(dest_clk),     // 1-bit input: Destination clock.
   .dest_rst(dest_rst),     // 1-bit input: optional; required when RST_USED = 1
   .src_clk(src_clk),       // 1-bit input: Source clock.
   .src_pulse(src_pulse),   // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
                            // destination clock domain. The minimum gap between each pulse transfer must be
                            // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
                            // between the falling edge of a src_pulse to the rising edge of the next
                            // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
                            // will generate a pulse the size of one dest_clk period in the destination
                            // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
                            // src_rst and/or dest_rst are asserted.

   .src_rst(src_rst)        // 1-bit input: optional; required when RST_USED = 1
);

// End of xpm_cdc_pulse_inst instantiation

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