ODDRE1 - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Primitive: Dedicated Double Data Rate (DDR) Output Register

  • PRIMITIVE_GROUP: REGISTER
  • PRIMITIVE_SUBGROUP: DDR
  • Families: UltraScale, UltraScale+

Introduction

In component mode, the ODDRE1 in UltraScale devices is a dedicated output register for use in transmitting double data rate (DDR) signals from FPGA devices. The ODDRE1 interface with the device fabric is limited to the same clock edges. This feature allows designers to avoid additional timing complexities and CLB usage.
Note: ODDRE1 components used in a design are translated and implemented by the Vivado design tools as OSERDESE3 components.

Port Descriptions

Port Direction Width Function
C Input 1 High-speed clock input.
D1 Input 1 Parallel data input 1.
D2 Input 1 Parallel data input 2.
Q Output 1 Data output to IOB.
SR Input 1 Active-High Asynchronous Reset.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Yes

Available Attributes

Attribute Type Allowed Values Default Description
IS_C_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the clock C pin is active-High or active-Low.
IS_D1_INVERTED BINARY 1'b0 to 1'b1 1'b0 Unsupported, do not use.
IS_D2_INVERTED BINARY 1'b0 to 1'b1 1'b0 Unsupported, do not use.
SIM_DEVICE STRING "7SERIES", "ULTRASCALE" "ULTRASCALE" Set the device version for simulation functionality.
SRVAL BINARY 1'b0, 1'b1 1'b0 Initializes the ODDRE1 Flip-Flops to the specified value.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- ODDRE1: Dedicated Double Data Rate (DDR) Output Register
--         UltraScale
-- Xilinx HDL Language Template, version 2024.1

ODDRE1_inst : ODDRE1
generic map (
   IS_C_INVERTED => '0',            -- Optional inversion for C
   IS_D1_INVERTED => '0',           -- Unsupported, do not use
   IS_D2_INVERTED => '0',           -- Unsupported, do not use
   SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version for simulation functionality (ULTRASCALE,
                                    -- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
   SRVAL => '0'                     -- Initializes the ODDRE1 Flip-Flops to the specified value ('0', '1')
)
port map (
   Q => Q,   -- 1-bit output: Data output to IOB
   C => C,   -- 1-bit input: High-speed clock input
   D1 => D1, -- 1-bit input: Parallel data input 1
   D2 => D2, -- 1-bit input: Parallel data input 2
   SR => SR  -- 1-bit input: Active-High Async Reset
);

-- End of ODDRE1_inst instantiation

Verilog Instantiation Template


// ODDRE1: Dedicated Double Data Rate (DDR) Output Register
//         UltraScale
// Xilinx HDL Language Template, version 2024.1

ODDRE1 #(
   .IS_C_INVERTED(1'b0),           // Optional inversion for C
   .IS_D1_INVERTED(1'b0),          // Unsupported, do not use
   .IS_D2_INVERTED(1'b0),          // Unsupported, do not use
   .SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE,
                                   // ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
   .SRVAL(1'b0)                    // Initializes the ODDRE1 Flip-Flops to the specified value (1'b0, 1'b1)
)
ODDRE1_inst (
   .Q(Q),   // 1-bit output: Data output to IOB
   .C(C),   // 1-bit input: High-speed clock input
   .D1(D1), // 1-bit input: Parallel data input 1
   .D2(D2), // 1-bit input: Parallel data input 2
   .SR(SR)  // 1-bit input: Active-High Async Reset
);

// End of ODDRE1_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)