MASTER_JTAG - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Primitive: JTAG Port Access

  • PRIMITIVE_GROUP: CONFIGURATION
  • PRIMITIVE_SUBGROUP: MASTER_JTAG
  • Families: UltraScale, UltraScale+

Introduction

This component is only intended for advanced secure applications, such as any combination of AES key programming (BBRAM or EFUSE), USER EFUSE programming during runtime, and where external JTAG access is prohibited. This component is not recommended when external JTAG port access is needed (that is, Vivado Device Programmer/ILA programming or debug tools) because the component is used to override the external JTAG pins of the device, allowing full access to the JTAG port from within the device. Once instantiated, the external JTAG port is completely disabled.

Port Descriptions

Port Direction Width Function
TCK Input 1 JTAG TCK input pin.
TDI Input 1 JTAG TDI input pin.
TDO Output 1 JTAG TDO output pin.
TMS Input 1 JTAG TMS input pin.

Design Entry Method

Instantiation Recommended
Inference No
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- MASTER_JTAG: JTAG Port Access
--              UltraScale
-- Xilinx HDL Language Template, version 2024.1

MASTER_JTAG_inst : MASTER_JTAG
port map (
   TDO => TDO, -- 1-bit output: JTAG TDO output pin.
   TCK => TCK, -- 1-bit input: JTAG TCK input pin.
   TDI => TDI, -- 1-bit input: JTAG TDI input pin.
   TMS => TMS  -- 1-bit input: JTAG TMS input pin.
);

-- End of MASTER_JTAG_inst instantiation

Verilog Instantiation Template


// MASTER_JTAG: JTAG Port Access
//              UltraScale
// Xilinx HDL Language Template, version 2024.1

MASTER_JTAG MASTER_JTAG_inst (
   .TDO(TDO), // 1-bit output: JTAG TDO output pin.
   .TCK(TCK), // 1-bit input: JTAG TCK input pin.
   .TDI(TDI), // 1-bit input: JTAG TDI input pin.
   .TMS(TMS)  // 1-bit input: JTAG TMS input pin.
);

// End of MASTER_JTAG_inst instantiation

Related Information

  • UltraScale Architecture Configuration User Guide (UG570)