IOBUF_DCIEN - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Primitive: Input/Output Buffer DCI Enable

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: BIDIR_BUFFER
  • Families: UltraScale, UltraScale+

Introduction

The IOBUF_DCIEN primitive is available in the HP I/O banks. It has an IBUFDISABLE port that can be used to disable the input buffer during periods that the buffer is not being used. The IOBUF_DCIEN primitive also has a DCITERMDISABLE port that can be used to manually disable the optional on-die receiver termination features (uncalibrated and DCI). See the UltraScale Architecture SelectIO Resources User Guide (UG571), "DCI Only available in the HP I/O Banks" and "Uncalibrated Input Termination in I/O Banks" sections for more details.

The IOBUF_DCIEN primitive can disable the input buffer and force the O output to the internal logic to a logic-Low when the IBUFDISABLE signal is asserted High and output buffer is 3-stated (T = High). If the I/O is using any on-die receiver termination features (uncalibrated and DCI), this primitive disables the termination legs whenever the DCITERMDISABLE signal is asserted High and the output buffer is 3-stated (T = High). When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination (uncalibrated or DCI) are controlled by IBUFDISABLE and DCITERMDISABLE, respectively. The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for this primitive to have the expected behavior that is specific to the architecture. When the output buffer is not 3-stated (T = Low), the input buffer and any on-die receiver termination (uncalibrated or DCI) are disabled and the O output (to the internal logic) is forced to a logic-Low. These features can be combined to reduce power whenever the input is idle for a period of time.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DRIVE, and SLEW, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
DCITERMDISABLE Input 1 Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.
I Input 1 Input of OBUF. Connect to the logic driving the output port.
IBUFDISABLE Input 1 Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
IO Inout 1 Bidirectional port to be connected directly to top-level inout port.
O Output 1 Output path of the buffer.
T Input 1 3-state enable input signifying whether the buffer acts as an input or output.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
SIM_DEVICE STRING "7SERIES", "ULTRASCALE" "7SERIES" Set the device version for simulation functionality.
USE_IBUFDISABLE STRING "TRUE", "FALSE", "T_CONTROL" "TRUE" Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IOBUF_DCIEN: Input/Output Buffer DCI Enable
--              UltraScale
-- Xilinx HDL Language Template, version 2024.1

IOBUF_DCIEN_inst : IOBUF_DCIEN
generic map (
   SIM_DEVICE => "ULTRASCALE", -- Set the device version for simulation functionality (ULTRASCALE)
   USE_IBUFDISABLE => "TRUE"   -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
port map (
   O => O,                           -- 1-bit output: Buffer output
   DCITERMDISABLE => DCITERMDISABLE, -- 1-bit input: DCI Termination Disable
   I => I,                           -- 1-bit input: Buffer input
   IBUFDISABLE => IBUFDISABLE,       -- 1-bit input: Buffer disable input, high=disable
   IO => IO,                         -- 1-bit inout: Buffer inout (connect directly to top-level port)
   T => T                            -- 1-bit input: 3-state enable input
);

-- End of IOBUF_DCIEN_inst instantiation

Verilog Instantiation Template


// IOBUF_DCIEN: Input/Output Buffer DCI Enable
//              UltraScale
// Xilinx HDL Language Template, version 2024.1

IOBUF_DCIEN #(
   .SIM_DEVICE("ULTRASCALE"), // Set the device version for simulation functionality (ULTRASCALE)
   .USE_IBUFDISABLE("TRUE")   // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
IOBUF_DCIEN_inst (
   .O(O),                           // 1-bit output: Buffer output
   .DCITERMDISABLE(DCITERMDISABLE), // 1-bit input: DCI Termination Disable
   .I(I),                           // 1-bit input: Buffer input
   .IBUFDISABLE(IBUFDISABLE),       // 1-bit input: Buffer disable input, high=disable
   .IO(IO),                         // 1-bit inout: Buffer inout (connect directly to top-level port)
   .T(T)                            // 1-bit input: 3-state enable input
);

// End of IOBUF_DCIEN_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)
  • Vivado Design Suite Properties Reference Guide (UG912)