PULLDOWN - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Primitive: I/O Pulldown

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: WEAK_DRIVER
  • Families: UltraScale, UltraScale+

Introduction

The design element is a weak pulldown element that pulls an undriven I/O to a logic zero state. For example, if the I/O is 3-stated and not driven by any other element, a logic 0 will exist on the I/O.

Port Descriptions

Port Direction Width Function
O Output 1 Pulldown output. Connect directly to a top-level port in the design.

Design Entry Method

Instantiation Yes
Inference Yes, via property
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- PULLDOWN: I/O Pulldown
--           UltraScale
-- Xilinx HDL Language Template, version 2024.1

PULLDOWN_inst : PULLDOWN
port map (
   O => O  -- 1-bit output: Pulldown output (connect directly to top-level port)
);

-- End of PULLDOWN_inst instantiation

Verilog Instantiation Template


// PULLDOWN: I/O Pulldown
//           UltraScale
// Xilinx HDL Language Template, version 2024.1

PULLDOWN PULLDOWN_inst (
   .O(O)  // 1-bit output: Pulldown output (connect directly to top-level port)
);

// End of PULLDOWN_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)