OBUF - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Primitive: Output Buffer

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: OUTPUT_BUFFER
  • Families: UltraScale, UltraScale+

Introduction

An output buffer (OBUF) must be used to drive signals from the device to external output pads.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DRIVE, and SLEW, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
I Input 1 Input of OBUF. Connect to the logic driving the output port.
O Output 1 Output of OBUF to be connected directly to top-level output port.

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- OBUF: Output Buffer
--       UltraScale
-- Xilinx HDL Language Template, version 2024.1

OBUF_inst : OBUF
port map (
   O => O, -- 1-bit output: Buffer output (connect directly to top-level port)
   I => I  -- 1-bit input: Buffer input
);

-- End of OBUF_inst instantiation

Verilog Instantiation Template


// OBUF: Output Buffer
//       UltraScale
// Xilinx HDL Language Template, version 2024.1

OBUF OBUF_inst (
   .O(O), // 1-bit output: Buffer output (connect directly to top-level port)
   .I(I)  // 1-bit input: Buffer input
);

// End of OBUF_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)
  • Vivado Design Suite Properties Reference Guide (UG912)