XPM_FIFO_SYNC - 2024.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2024-05-30
Version
2024.1 English

Parameterized Macro: Synchronous FIFO

  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: XPM_FIFO
  • Families: UltraScale, UltraScale+

Introduction

This macro is used to instantiate synchronous FIFO.

The following describes the basic write and read operation of an XPM_FIFO instance.
  • All synchronous signals are sensitive to the rising edge of wr_clk, which is assumed to be a buffered and toggling clock signal behaving according to target device and FIFO/memory primitive requirements.
  • A write operation is performed when the FIFO is not full and wr_en is asserted on each wr_clk cycle.
  • A read operation is performed when the FIFO is not empty and rd_en is asserted on each wr_clk cycle.
  • The number of clock cycles required for XPM FIFO to react to dout, full and empty changes depends on the CLOCK_DOMAIN, READ_MODE, and FIFO_READ_LATENCY settings.
    • It might take more than one wr_clk cycle to deassert empty due to write operation (wr_en = 1).
    • It might take more than one wr_clk cycle to present the read data on dout port upon assertion of rd_en.
    • It might take more than one wr_clk cycle to deassert full due to read operation (rd_en = 1).
  • All write operations are gated by the value of wr_en and full on the initiating wr_clk cycle.
  • All read operations are gated by the value of rd_en and empty on the initiating wr_clk cycle.
  • Undriven or unknown values provided on module inputs will produce undefined output port behavior.
  • wr_en/rd_en should not be toggled when reset (rst) or wr_rst_busy or rd_rst_busy is asserted.
  • Assertion/deassertion of prog_full happens only when full is deasserted.
  • Assertion/deassertion of prog_empty happens only when empty is deasserted.

Timing Diagrams

Figure 1. Reset Behavior

Figure 2. Standard Write Operation. FIFO_WRITE_DEPTH=16, PROG_FULL_THRESH=6

Figure 3. Standard Read Operation. FIFO_WRITE_DEPTH=16, PROG_EMPTY_THRESH=3, FIFO_READ_LATENCY=1

Figure 4. Standard Read Operation. FIFO_WRITE_DEPTH=16, PROG_EMPTY_THRESH=3, FIFO_READ_LATENCY=3

Figure 5. Write Operation. READ_MODE=FWFT, FIFO_WRITE_DEPTH=16, PROG_FULL_THRESH=7

Figure 6. Read Operation. READ_MODE=FWFT, FIFO_WRITE_DEPTH=16, PROG_EMPTY_THRESH=5

Figure 7. Standard Write Operation with Empty Deassertion. FIFO_WRITE_DEPTH=16

Figure 8. Standard Read Operation with Full Deassertion. FIFO_WRITE_DEPTH=16, FIFO_READ_LATENCY=1

Port Descriptions

Port Direction Width Domain Sense Handling if Unused Function
almost_empty Output 1 wr_clk LEVEL_HIGH DoNotCare Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to empty.
almost_full Output 1 wr_clk LEVEL_HIGH DoNotCare Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.
data_valid Output 1 wr_clk LEVEL_HIGH DoNotCare Read Data Valid: When asserted, this signal indicates that valid data is available on the output bus (dout).
dbiterr Output 1 wr_clk LEVEL_HIGH DoNotCare Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.
din Input WRITE_DATA_WIDTH wr_clk NA Active Write Data: The input data bus used when writing the FIFO.
dout Output READ_DATA_WIDTH wr_clk NA Active Read Data: The output data bus is driven when reading the FIFO.
empty Output 1 wr_clk LEVEL_HIGH Active

Empty Flag: When asserted, this signal indicates that the FIFO is empty.

Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO.

full Output 1 wr_clk LEVEL_HIGH Active

Full Flag: When asserted, this signal indicates that the FIFO is full.

Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive to the contents of the FIFO.

injectdbiterr Input 1 wr_clk LEVEL_HIGH 0 Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or UltraRAM macros.
injectsbiterr Input 1 wr_clk LEVEL_HIGH 0 Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or UltraRAM macros.
overflow Output 1 wr_clk LEVEL_HIGH DoNotCare Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected, because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO.
prog_empty Output 1 wr_clk LEVEL_HIGH DoNotCare

Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable empty threshold value.

It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value.

prog_full Output 1 wr_clk LEVEL_HIGH DoNotCare

Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable full threshold value.

It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value.

rd_data_count Output RD_DATA_COUNT_WIDTH wr_clk NA DoNotCare Read Data Count: This bus indicates the number of words read from the FIFO.
rd_en Input 1 wr_clk LEVEL_HIGH Active Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO.
  • Must be held active-low when rd_rst_busy is active high.
rd_rst_busy Output 1 wr_clk LEVEL_HIGH DoNotCare Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state.
rst Input 1 wr_clk LEVEL_HIGH Active Reset: Must be synchronous to wr_clk. The clock(s) can be unstable at the time of applying reset, but reset must be released only after the clock(s) is/are stable.
sbiterr Output 1 wr_clk LEVEL_HIGH DoNotCare Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.
sleep Input 1 NA LEVEL_HIGH 0 Dynamic power saving- If sleep is High, the memory/fifo block is in power saving mode.
underflow Output 1 wr_clk LEVEL_HIGH DoNotCare Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected because the FIFO is empty. Under flowing the FIFO is not destructive to the FIFO.
wr_ack Output 1 wr_clk LEVEL_HIGH DoNotCare Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle is succeeded.
wr_clk Input 1 NA EDGE_RISING Active Write clock: Used for write operation. wr_clk must be a free running clock.
wr_data_count Output WR_DATA_COUNT_WIDTH wr_clk NA DoNotCare Write Data Count: This bus indicates the number of words written into the FIFO.
wr_en Input 1 wr_clk LEVEL_HIGH Active Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO
  • Must be held active-low when rst or wr_rst_busy or rd_rst_busy is active high
wr_rst_busy Output 1 wr_clk LEVEL_HIGH DoNotCare Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
CASCADE_HEIGHT DECIMAL 0 to 64 0

0- No Cascade Height, Allow Vivado Synthesis to choose.

1 or more - Vivado Synthesis sets the specified value as Cascade Height.

DOUT_RESET_VALUE STRING String "0" Reset value of read data path.
ECC_MODE STRING "no_ecc", "en_ecc" "no_ecc"
  • "no_ecc" - Disables ECC
  • "en_ecc" - Enables both ECC Encoder and Decoder
NOTE: ECC_MODE should be "no_ecc" if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.
FIFO_MEMORY_TYPE STRING "auto", "block", "distributed", "ultra" "auto" Designate the fifo memory primitive (resource type) to use-
  • "auto"- Allow Vivado Synthesis to choose
  • "block"- Block RAM FIFO
  • "distributed"- Distributed RAM FIFO
  • "ultra"- URAM FIFO
NOTE: There may be a behavior mismatch if Block RAM or Ultra RAM specific features, like ECC or Asymmetry, are selected with FIFO_MEMORY_TYPE set to "auto".
FIFO_READ_LATENCY DECIMAL 0 to 100 1 Number of output register stages in the read data path
  • If READ_MODE = "fwft", then the only applicable value is 0
FIFO_WRITE_DEPTH DECIMAL 16 to 4194304 2048 Defines the FIFO Write Depth, must be power of two
  • In standard READ_MODE, the effective depth = FIFO_WRITE_DEPTH
  • In First-Word-Fall-Through READ_MODE, the effective depth = FIFO_WRITE_DEPTH+2
NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits.
FULL_RESET_VALUE DECIMAL 0 to 1 0 Sets full, almost_full and prog_full to FULL_RESET_VALUE during reset
PROG_EMPTY_THRESH DECIMAL 3 to 4194304 10

Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted.

  • Min_Value = 3 + (READ_MODE_VAL*2)
  • Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2)

If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1.

NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is changed, ensure the threshold value is within the valid range though the programmable flags are not used.
PROG_FULL_THRESH DECIMAL 3 to 4194301 10

Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted.

  • Min_Value = 3 + (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH))
  • Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH))

If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1.

NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is changed, ensure the threshold value is within the valid range though the programmable flags are not used.
RD_DATA_COUNT_WIDTH DECIMAL 1 to 23 1 Specifies the width of rd_data_count. To reflect the correct value, the width should be log2(FIFO_READ_DEPTH)+1.
  • FIFO_READ_DEPTH = FIFO_WRITE_DEPTH*WRITE_DATA_WIDTH/READ_DATA_WIDTH
READ_DATA_WIDTH DECIMAL 1 to 4096 32 Defines the width of the read data port, dout
  • Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1
  • For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4.
NOTE:
  • READ_DATA_WIDTH should be equal to WRITE_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.
  • The maximum FIFO size (width x depth) is limited to 150-Megabits.
READ_MODE STRING "std", "fwft" "std"
  • "std"- standard read mode
  • "fwft"- First-Word-Fall-Through read mode
SIM_ASSERT_CHK DECIMAL 0 to 1 0

0- Disable simulation message reporting. Messages related to potential misuse will not be reported.

1- Enable simulation message reporting. Messages related to potential misuse will be reported.

USE_ADV_FEATURES STRING String "0707"

Enables data_valid, almost_empty, rd_data_count, prog_empty, underflow, wr_ack, almost_full, wr_data_count, prog_full, overflow features.

  • Setting USE_ADV_FEATURES[0] to 1 enables overflow flag; Default value of this bit is 1
  • Setting USE_ADV_FEATURES[1] to 1 enables prog_full flag; Default value of this bit is 1
  • Setting USE_ADV_FEATURES[2] to 1 enables wr_data_count; Default value of this bit is 1
  • Setting USE_ADV_FEATURES[3] to 1 enables almost_full flag; Default value of this bit is 0
  • Setting USE_ADV_FEATURES[4] to 1 enables wr_ack flag; Default value of this bit is 0
  • Setting USE_ADV_FEATURES[8] to 1 enables underflow flag; Default value of this bit is 1
  • Setting USE_ADV_FEATURES[9] to 1 enables prog_empty flag; Default value of this bit is 1
  • Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count; Default value of this bit is 1
  • Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0
  • Setting USE_ADV_FEATURES[12] to 1 enables data_valid flag; Default value of this bit is 0
WAKEUP_TIME DECIMAL 0 to 2 0
  • 0 - Disable sleep
  • 2 - Use Sleep Pin
NOTE: WAKEUP_TIME should be 0 if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.
WR_DATA_COUNT_WIDTH DECIMAL 1 to 23 1 Specifies the width of wr_data_count. To reflect the correct value, the width should be log2(FIFO_WRITE_DEPTH)+1.
WRITE_DATA_WIDTH DECIMAL 1 to 4096 32 Defines the width of the write data port, din
  • Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1
  • For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4.
NOTE:
  • WRITE_DATA_WIDTH should be equal to READ_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.
  • The maximum FIFO size (width x depth) is limited to 150-Megabits.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library xpm;
use xpm.vcomponents.all;

-- xpm_fifo_sync: Synchronous FIFO
-- Xilinx Parameterized Macro, version 2024.1

xpm_fifo_sync_inst : xpm_fifo_sync
generic map (
   CASCADE_HEIGHT => 0,            -- DECIMAL
   DOUT_RESET_VALUE => "0",        -- String
   ECC_MODE => "no_ecc",           -- String
   EN_SIM_ASSERT_ERR => "warning", -- String
   FIFO_MEMORY_TYPE => "auto",     -- String
   FIFO_READ_LATENCY => 1,         -- DECIMAL
   FIFO_WRITE_DEPTH => 2048,       -- DECIMAL
   FULL_RESET_VALUE => 0,          -- DECIMAL
   PROG_EMPTY_THRESH => 10,        -- DECIMAL
   PROG_FULL_THRESH => 10,         -- DECIMAL
   RD_DATA_COUNT_WIDTH => 1,       -- DECIMAL
   READ_DATA_WIDTH => 32,          -- DECIMAL
   READ_MODE => "std",             -- String
   SIM_ASSERT_CHK => 0,            -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   USE_ADV_FEATURES => "0707",     -- String
   WAKEUP_TIME => 0,               -- DECIMAL
   WRITE_DATA_WIDTH => 32,         -- DECIMAL
   WR_DATA_COUNT_WIDTH => 1        -- DECIMAL
)
port map (
   almost_empty => almost_empty,   -- 1-bit output: Almost Empty : When asserted, this signal indicates that
                                   -- only one more read can be performed before the FIFO goes to empty.

   almost_full => almost_full,     -- 1-bit output: Almost Full: When asserted, this signal indicates that
                                   -- only one more write can be performed before the FIFO is full.

   data_valid => data_valid,       -- 1-bit output: Read Data Valid: When asserted, this signal indicates
                                   -- that valid data is available on the output bus (dout).

   dbiterr => dbiterr,             -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
                                   -- detected a double-bit error and data in the FIFO core is corrupted.

   dout => dout,                   -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
                                   -- when reading the FIFO.

   empty => empty,                 -- 1-bit output: Empty Flag: When asserted, this signal indicates that
                                   -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
                                   -- initiating a read while empty is not destructive to the FIFO.

   full => full,                   -- 1-bit output: Full Flag: When asserted, this signal indicates that the
                                   -- FIFO is full. Write requests are ignored when the FIFO is full,
                                   -- initiating a write when the FIFO is full is not destructive to the
                                   -- contents of the FIFO.

   overflow => overflow,           -- 1-bit output: Overflow: This signal indicates that a write request
                                   -- (wren) during the prior clock cycle was rejected, because the FIFO is
                                   -- full. Overflowing the FIFO is not destructive to the contents of the
                                   -- FIFO.

   prog_empty => prog_empty,       -- 1-bit output: Programmable Empty: This signal is asserted when the
                                   -- number of words in the FIFO is less than or equal to the programmable
                                   -- empty threshold value. It is de-asserted when the number of words in
                                   -- the FIFO exceeds the programmable empty threshold value.

   prog_full => prog_full,         -- 1-bit output: Programmable Full: This signal is asserted when the
                                   -- number of words in the FIFO is greater than or equal to the
                                   -- programmable full threshold value. It is de-asserted when the number
                                   -- of words in the FIFO is less than the programmable full threshold
                                   -- value.

   rd_data_count => rd_data_count, -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
                                   -- the number of words read from the FIFO.

   rd_rst_busy => rd_rst_busy,     -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
                                   -- read domain is currently in a reset state.

   sbiterr => sbiterr,             -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
                                   -- detected and fixed a single-bit error.

   underflow => underflow,         -- 1-bit output: Underflow: Indicates that the read request (rd_en)
                                   -- during the previous clock cycle was rejected because the FIFO is
                                   -- empty. Under flowing the FIFO is not destructive to the FIFO.

   wr_ack => wr_ack,               -- 1-bit output: Write Acknowledge: This signal indicates that a write
                                   -- request (wr_en) during the prior clock cycle is succeeded.

   wr_data_count => wr_data_count, -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
                                   -- the number of words written into the FIFO.

   wr_rst_busy => wr_rst_busy,     -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
                                   -- write domain is currently in a reset state.

   din => din,                     -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
                                   -- writing the FIFO.

   injectdbiterr => injectdbiterr, -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
                                   -- the ECC feature is used on block RAMs or UltraRAM macros.

   injectsbiterr => injectsbiterr, -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
                                   -- the ECC feature is used on block RAMs or UltraRAM macros.

   rd_en => rd_en,                 -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
                                   -- signal causes data (on dout) to be read from the FIFO. Must be held
                                   -- active-low when rd_rst_busy is active high.

   rst => rst,                     -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
                                   -- unstable at the time of applying reset, but reset must be released
                                   -- only after the clock(s) is/are stable.

   sleep => sleep,                 -- 1-bit input: Dynamic power saving- If sleep is High, the memory/fifo
                                   -- block is in power saving mode.

   wr_clk => wr_clk,               -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
                                   -- free running clock.

   wr_en => wr_en                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
                                   -- signal causes data (on din) to be written to the FIFO Must be held
                                   -- active-low when rst or wr_rst_busy or rd_rst_busy is active high

);

-- End of xpm_fifo_sync_inst instantiation

Verilog Instantiation Template


// xpm_fifo_sync: Synchronous FIFO
// Xilinx Parameterized Macro, version 2024.1

xpm_fifo_sync #(
   .CASCADE_HEIGHT(0),            // DECIMAL
   .DOUT_RESET_VALUE("0"),        // String
   .ECC_MODE("no_ecc"),           // String
   .EN_SIM_ASSERT_ERR("warning"), // String
   .FIFO_MEMORY_TYPE("auto"),     // String
   .FIFO_READ_LATENCY(1),         // DECIMAL
   .FIFO_WRITE_DEPTH(2048),       // DECIMAL
   .FULL_RESET_VALUE(0),          // DECIMAL
   .PROG_EMPTY_THRESH(10),        // DECIMAL
   .PROG_FULL_THRESH(10),         // DECIMAL
   .RD_DATA_COUNT_WIDTH(1),       // DECIMAL
   .READ_DATA_WIDTH(32),          // DECIMAL
   .READ_MODE("std"),             // String
   .SIM_ASSERT_CHK(0),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   .USE_ADV_FEATURES("0707"),     // String
   .WAKEUP_TIME(0),               // DECIMAL
   .WRITE_DATA_WIDTH(32),         // DECIMAL
   .WR_DATA_COUNT_WIDTH(1)        // DECIMAL
)
xpm_fifo_sync_inst (
   .almost_empty(almost_empty),   // 1-bit output: Almost Empty : When asserted, this signal indicates that
                                  // only one more read can be performed before the FIFO goes to empty.

   .almost_full(almost_full),     // 1-bit output: Almost Full: When asserted, this signal indicates that
                                  // only one more write can be performed before the FIFO is full.

   .data_valid(data_valid),       // 1-bit output: Read Data Valid: When asserted, this signal indicates
                                  // that valid data is available on the output bus (dout).

   .dbiterr(dbiterr),             // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected
                                  // a double-bit error and data in the FIFO core is corrupted.

   .dout(dout),                   // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
                                  // when reading the FIFO.

   .empty(empty),                 // 1-bit output: Empty Flag: When asserted, this signal indicates that the
                                  // FIFO is empty. Read requests are ignored when the FIFO is empty,
                                  // initiating a read while empty is not destructive to the FIFO.

   .full(full),                   // 1-bit output: Full Flag: When asserted, this signal indicates that the
                                  // FIFO is full. Write requests are ignored when the FIFO is full,
                                  // initiating a write when the FIFO is full is not destructive to the
                                  // contents of the FIFO.

   .overflow(overflow),           // 1-bit output: Overflow: This signal indicates that a write request
                                  // (wren) during the prior clock cycle was rejected, because the FIFO is
                                  // full. Overflowing the FIFO is not destructive to the contents of the
                                  // FIFO.

   .prog_empty(prog_empty),       // 1-bit output: Programmable Empty: This signal is asserted when the
                                  // number of words in the FIFO is less than or equal to the programmable
                                  // empty threshold value. It is de-asserted when the number of words in
                                  // the FIFO exceeds the programmable empty threshold value.

   .prog_full(prog_full),         // 1-bit output: Programmable Full: This signal is asserted when the
                                  // number of words in the FIFO is greater than or equal to the
                                  // programmable full threshold value. It is de-asserted when the number of
                                  // words in the FIFO is less than the programmable full threshold value.

   .rd_data_count(rd_data_count), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the
                                  // number of words read from the FIFO.

   .rd_rst_busy(rd_rst_busy),     // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read
                                  // domain is currently in a reset state.

   .sbiterr(sbiterr),             // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected
                                  // and fixed a single-bit error.

   .underflow(underflow),         // 1-bit output: Underflow: Indicates that the read request (rd_en) during
                                  // the previous clock cycle was rejected because the FIFO is empty. Under
                                  // flowing the FIFO is not destructive to the FIFO.

   .wr_ack(wr_ack),               // 1-bit output: Write Acknowledge: This signal indicates that a write
                                  // request (wr_en) during the prior clock cycle is succeeded.

   .wr_data_count(wr_data_count), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
                                  // the number of words written into the FIFO.

   .wr_rst_busy(wr_rst_busy),     // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
                                  // write domain is currently in a reset state.

   .din(din),                     // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
                                  // writing the FIFO.

   .injectdbiterr(injectdbiterr), // 1-bit input: Double Bit Error Injection: Injects a double bit error if
                                  // the ECC feature is used on block RAMs or UltraRAM macros.

   .injectsbiterr(injectsbiterr), // 1-bit input: Single Bit Error Injection: Injects a single bit error if
                                  // the ECC feature is used on block RAMs or UltraRAM macros.

   .rd_en(rd_en),                 // 1-bit input: Read Enable: If the FIFO is not empty, asserting this
                                  // signal causes data (on dout) to be read from the FIFO. Must be held
                                  // active-low when rd_rst_busy is active high.

   .rst(rst),                     // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
                                  // unstable at the time of applying reset, but reset must be released only
                                  // after the clock(s) is/are stable.

   .sleep(sleep),                 // 1-bit input: Dynamic power saving- If sleep is High, the memory/fifo
                                  // block is in power saving mode.

   .wr_clk(wr_clk),               // 1-bit input: Write clock: Used for write operation. wr_clk must be a
                                  // free running clock.

   .wr_en(wr_en)                  // 1-bit input: Write Enable: If the FIFO is not full, asserting this
                                  // signal causes data (on din) to be written to the FIFO Must be held
                                  // active-low when rst or wr_rst_busy or rd_rst_busy is active high

);

// End of xpm_fifo_sync_inst instantiation

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