System Debug Planning - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

The AMD Versalâ„¢ adaptive SoC includes a debug architecture that enables enhanced system debug methodology capabilities. This debug architecture is designed to work in any environment, including the lab, data center, and edge computing environments. For more information on debugging, see this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).

The Versal adaptive SoC debug architecture consists of a centralized debug packet controller (DPC), which is the packet processing engine of the debug architecture. The packets that are processed by the DPC are referred to as the debug and trace packets (DTP). These packets are decoded by the DPC to determine the commands, the destinations, and any potential higher-level flow control and management tasks. The DPC processes the DTP sent by a host, executes any commands embedded in the packets, and generates responses that are sent back to the host. For more information on the DPC, see this link in the Versal Adaptive SoC Technical Reference Manual (AM011).

Note: When booting securely, JTAG is disabled by default. For additional details, see the Versal Adaptive SoC Security Manual (UG1508). This manual requires an active NDA to download from the Design Security Lounge.