Memory Hierarchy - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

For data-intensive applications that demand high-bandwidth memory, the best approach is to construct an application-specific memory hierarchy, such as memory caching from DDR memory to PL RAMs (UltraRAM/BRAM). Versal devices can access the DDR memory through the NoC. The DDR memory is connected to the device fabric, and the Arm Cortex-A72 and the AI Engines are connected through the NoC. Using DMA data movers in the PL, you can coordinate data movement to and from the hard IP to the DDR memory, leveraging the intermediate PL RAM stages for caching or data buffering.

Note: Versal devices also support soft memory controllers as in previous architectures.

Versal devices provide access to DDR memory using DMAs. The DDR memory is connected to the device fabric and other hard IP through the hard memory controller and NoC. You can use DMA data movers in the PL to coordinate data movement to and from the DDR memory. You can also configure the NoC for maximum bandwidth using the DDR memory controllers available on the Versal device.

Tip: Use the NoC compiler to find the optimal solution for a required aggregate bandwidth.