Debug via JTAG - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

The PMC includes a JTAG interface that can be used for both programming and debugging designs running on the Versal adaptive SoC. The JTAG interface consists of two cascaded blocks: the debug access port (DAP) and test access port (TAP). The DAP is primarily used to access the various debug features of the PS and can also be used for low-bandwidth read/write access to any accessible register and memory location within the address range of the PS. The TAP interface is primarily used for accessing the device configuration and boundary scan infrastructure, and also includes instructions for configuring and accessing the DPC functionality.