DDR Memory Usage - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

When targeting Versal adaptive SoCs, focus on usage, bandwidth, and performance expected from the integrated DDR memory controllers in the device. For example, image processing uses a large amount of data (e.g., data for the image, weights, layers, etc.), which all require different bandwidths at different points in time. These kinds of applications have a significant usage of DDR memory, including impact on the DDR memory bandwidth and latency. Depending on the type of application and its memory bandwidth and performance requirements, you need to have a fairly accurate understanding of the QoS requirements on the traffic generated by the application.

Another important consideration to make regarding DDR memory usage includes the impact of memory partitioning. Based on your application bandwidth needs as well as demands on the DDR memory, it might be optimal to either interleave the memory across multiple DDRs or treat multiple DDR memory controllers as independent. For DDR memory controller-NoC configuration guidelines, see this link Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).