Debug via Aurora (HSDP) - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-06-19
Version
2024.1 English

The PS includes an integrated Aurora 64B/66B block that is dedicated for use in accessing the DPC via a high-speed GT-based interface. This protocol to access DPC is called High-Speed Debug Port (HSDP). HSDP provides bidirectional access to the device from an external host debug/trace module, allowing for high-speed debug and trace operations. You can connect the SmartLynq+ module to the Aurora interface to access the HSDP in the Versal adaptive SoC. For more information, see this link in the SmartLynq+ Module User Guide (UG1514). For information on HSDP quad availability, see this link in the Versal Adaptive SoC Technical Reference Manual (AM011).

Note: The integrated HSDP Aurora interface is not available in all Versal adaptive SoCs. This interface requires additional configuration in the Control, Interfaces, and Processing (CIPS) IP and the use of additional Gigabit Transceivers.