HBM Memory Usage - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

The AMD Versalâ„¢ HBM series contains up to two HBM2e memory stacks of up to 16 GB each and an integrated AXI HBM controller. As is the case with DDR memory, you should focus on usage, bandwidth, and performance expected from the HBM controller. The HBM controller works together with the NoC and hence you need to understand the NoC architecture to make the most of the HBM memory on the devices. HBM has a wide variety of applications such as machine learning, database acceleration, next-generation firewalls, aerospace, defense, and advanced network testers. The Versal HBM series provides massive parallel processing capability and enormous memory bandwidth through the integrated HBM.

To apply the maximum processing and performance, model the NoC dataflow using the AXI traffic generator IP which suits the data pattern desired by the application. To receive the best possible throughput out of the HBM for the application, you should understand NoC architecture and factors. A few of the considerations to make regarding the performance would be HBM operating frequency, transaction sizes, frequency of the AXI ports, and address mapping for HBM. See the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) to learn more about the HBM controller and its usage guidelines.