Selecting the Debug Interfaces - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

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2024.1 English

The Versal architecture offers multiple physical interfaces that can be used to connect a debugger to the DPC. The following table shows the debug interfaces recommended for different use cases.

Note: The various APUs and RPUs of the PS can be debugged via the Arm® CoreSight™ infrastructure that is integrated into the PS. The CoreSight infrastructure is accessible via the JTAG-DAP, HSDP, PL, and PCIe® interfaces. For more information, see this link in the Versal Adaptive SoC Technical Reference Manual (AM011).
Table 1. Recommended Debug Interface Based on Debugging Goals
Recommended Debug Interface Debugging Goals Notes
  • Basic hardware debug using AXIS-ILA, AXIS-VIO, and other hardware debug cores
  • Small PDI download
Using JTAG allows low-speed connectivity to all debug cores in the design with no additional design modification
JTAG + HSDP (Aurora with SmartLynq+)
  • Advanced hardware debug using many AXIS-ILA, AXIS-VIO, and other hardware debug cores
  • Booting large Linux images without using SD card, initializing memory space using XSDB
  • Large PDI download
Using HSDP with the SmartLynq+ module enables debug connectivity that is much faster than JTAG with minimal design modification