Hardware-Only System Validation Planning - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

Hardware-only system designs typically include a processor core, hardened IP, and programmable logic (PL). You can use the following system-level debugging tools to diagnose the system-level issues in your design:

  • Xilinx System Debugger (XSDB)
  • AXI Streaming Integrated Logic Analyzer (AXIS-ILA)
  • AXI Streaming Virtual Input/Output (AXIS-VIO)
  • Integrated Bit Error Ratio Tester (IBERT)

The first step in system-level design debugging is to read the hardware status using XSDB tool and then use the tools listed in the following table to find the root cause of the issues.

Note: For information on XSDB commands, see the Software Command-Line Tool in the Vitis Embedded Software Development Flow Documentation (UG1400).
Table 1. Hardware-only System Debug Tools
Hardware Debug Tool
Processor-based system-level debug
  • XSDB
PL logic system debug
  • AXIS-ILA
  • AXIS-VIO
PL logic debug
  • IBERT
  • AXIS-ILA
  • AXIS-VIO
Hardened IP
  • IBERT
  • AXIS-ILA
  • AXIS-VIO
GT I/O hard block debug
  • IBERT