Planning for PL and Hard Block Debug - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

You might need to debug the programmable logic (PL) and hard blocks if you encounter situations that are difficult to replicate in PL logic simulation. The PL and hard blocks support logic debug using the following ChipScope™ debug IP cores and hard blocks:

AXI Streaming Integrated Logic Analyzer (AXIS-ILA)
The AXIS-ILA core allows you to perform in-system debugging of post-implemented designs by triggering on-hardware events and capturing data at design speeds.
AXI Streaming Virtual Input/Output (AXIS-VIO)
The AXIS-VIO core allows you to monitor and drive design signals in real time, taking the place of physical input or output elements such as switches or light-emitting diodes (LEDs).
Integrated Bit Error Ratio Tester (IBERT) GTY/GTYP
The Versal adaptive SoC GTY/GTYP contains built-in IBERT Serial Analyzer functionality that allows in-system serial I/O validation and debug. This solution requires no additional PL IP.
NoC DDR Memory Controller Calibration Debug
The DDR memory controller integrated into the Versal adaptive SoC NoC supports a calibration debug interface accessible through the AMD Vivado™ Hardware Manager.
PCI Express Link Debug
The Versal adaptive SoC PCI Express® Integrated Block supports a link debug interface. If enabled, you can view the Link Training and Status State Machine (LTSSM) state transitions in the Vivado Hardware Manager.