Simple Filter Chain Example - 2024.1 English

Versal Adaptive SoC System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2024-05-30
Version
2024.1 English

To illustrate throughput and latency considerations when working with FIR filters, the following example shows a channel filter followed by an interpolating half-band filter.

Figure 1. Simple Filter Chain Example
  • Implementation 1: Channel and Interpolation filter kernels placed into their own individual AI Engine tiles.

    The ping-pong buffers are just one deep to manage the data across the simple example.

    Figure 2. Graph View from Vitis Analyzer
  • Implementation 2: Channel filter is split across four AI Engines to improve the throughput.

    Notice how the data on the input needs additional buffering, including four ping-pong pairs, (green box) to service these four AI Engine kernels. However, the overall throughput increases as a result of this partitioning, and there is a trade-off to be made with respect to AI Engine resource utilization.

    Figure 3. Graph View Showing Channel Filter Split Across Four AI Engine Tiles